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Age
Commit message (
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Author
2018-10-01
arch-arm: Implement AArch64 ID regs as bitunions
Giacomo Travaglini
2018-10-01
arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register
Giacomo Travaglini
2018-10-01
arch-arm: Move MiscReg BitUnions into a separate header file
Giacomo Travaglini
2018-10-01
arch-arm: Init AArch64 ID registers in SE mode
Giacomo Travaglini
2018-09-28
arch-arm: raise/clear IRQ when writing to PMOVSCLR/SET
Giacomo Travaglini
2018-09-19
syscall_emul: expand AuxVector class
Brandon Potter
2018-09-13
Fix SConstruct for asan build
Earl Ou
2018-09-13
arch-arm: Correction for address size in EL1&0 translation
Anouk Van Laer
2018-09-13
arch-arm: Correction to address size in EL2/EL3
Anouk Van Laer
2018-09-12
dev-arm: rename Pl390 to GicV2
Ciro Santilli
2018-09-10
dev-arm: Factory SimObject for generating ArmInterruptPin
Giacomo Travaglini
2018-09-10
arm: Use the interrupt adaptor in the PMU
Andreas Sandberg
2018-09-10
arm: Add support for tracking TCs in ISA devices
Andreas Sandberg
2018-08-10
arm: Add support for RCpc load-acquire instructions (ARMv8.3)
Giacomo Gabrielli
2018-08-02
arch-arm: Don't fail to initialise PMU if BP is missing
Andreas Sandberg
2018-07-16
arch-arm: Introduce ARMv8.1 Virtual Timer System Registers
Giacomo Travaglini
2018-07-16
arch-arm: Introduce RAS System Registers
Giacomo Travaglini
2018-06-28
arch-arm: Fix incorrect t{0,1}sz field in TTBCR
Andreas Sandberg
2018-06-22
arch-arm: AArch32 execution triggering AArch64 SW Break
Giacomo Travaglini
2018-06-22
arch-arm: BadMode checking if corresponding EL is implemented
Giacomo Travaglini
2018-06-14
arch-arm: Adapting IllegalExecution fault for AArch32
Giacomo Travaglini
2018-06-14
arch-arm: Add Illegal Execution flag to PCState
Giacomo Travaglini
2018-06-14
arch-arm: Read APSR in User Mode
Giacomo Travaglini
2018-06-13
arch-arm: Fix missing Request allocation
Giacomo Travaglini
2018-06-11
misc: Using smart pointers for memory Requests
Giacomo Travaglini
2018-06-11
misc: Substitute pointer to Request with aliased RequestPtr
Giacomo Travaglini
2018-06-06
arch-arm: Remove dead doingStage2 variable in PT walker
Andreas Sandberg
2018-06-06
arch-arm: Perform stage 2 lookups using the EL2 state
Andreas Sandberg
2018-06-06
arch-arm: Respect EL from translation type
Andreas Sandberg
2018-06-06
arch-arm: Fix page size handling when merging stage 1 and 2
Andreas Sandberg
2018-06-06
dev, arm: Add support for HYP & secure timers
Andreas Sandberg
2018-06-06
arch-arm: Adjust breakpoint EC depending on source state
Andreas Sandberg
2018-05-29
arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP
Giacomo Travaglini
2018-05-29
arch-arm: Remove unusued MISCREG_A64_UNIMPL
Giacomo Travaglini
2018-05-29
arch-arm: MPIDR.MT = 1 in a multithreaded system
Giacomo Travaglini
2018-05-29
arch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation defined
Giacomo Travaglini
2018-05-29
arch-arm: Implement ARMv8.1 TTBR1_EL2 register
Giacomo Travaglini
2018-05-29
arch-arm: Add E2H bit to HCR_EL2 System register
Giacomo Travaglini
2018-05-16
arch-arm: Fix semihosting arg count for SYS_GET_CMDLINE
Andreas Sandberg
2018-05-16
arch-arm: Add support for semihosting STDIO redirection
Andreas Sandberg
2018-05-08
arch-arm: Map ID_x_EL1 registers to AArch32 version
Giacomo Travaglini
2018-04-27
sim,cpu,mem,arch: Introduced MasterInfo data structure
Giacomo Travaglini
2018-04-19
arch-arm: Add ARMv8.1 TTBR1_EL2 register
Giacomo Travaglini
2018-04-19
arch-arm: Fix Unknown Instruction disassemble
Giacomo Travaglini
2018-04-19
arch-arm: Change disassemble when MSR to UNKNOWN register
Giacomo Travaglini
2018-04-18
arch-arm: Fix masking in CPACR_EL1
Chuan Zhu
2018-04-18
arch-arm: Mask out unsupported trapped exception handling bits
Chuan Zhu
2018-04-18
arch-arm: Fix FPEXC32_EL2 to FPEXC mapping
Chuan Zhu
2018-04-18
arch-arm: Adding MiscReg Priv (EL1) global flag
Giacomo Travaglini
2018-04-18
arch-arm: Correct masking of cp10 and cp11 in CPACR
Chuan Zhu
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