summaryrefslogtreecommitdiff
path: root/src/arch/arm
AgeCommit message (Expand)Author
2019-04-11arch-arm: Enable PMSELR_EL0 read in PMUGiacomo Travaglini
2019-04-02dev-arm: Make GICv3 maintenance interrupt an ArmInterruptGiacomo Travaglini
2019-04-01dev-arm: Correct cast of template parameterAndrea Mondelli
2019-03-28arch-arm: Fix use of bitwise operators on booleansJavier Setoain
2019-03-28arch-arm: Fix index generation for VecElem operandsGiacomo Travaglini
2019-03-25arch-arm: Add missing fall-through defaultsJavier Setoain
2019-03-22sim-se: Fixed initialization array sizeTiago Muck
2019-03-21dev-arm: ambiguous use of getPort()Andrea Mondelli
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
2019-03-14arch-arm,cpu: Add initial support for Arm SVEGiacomo Gabrielli
2019-03-11arch-arm: Fixing implicit fallthrough build errorsRyan Gambord
2019-03-01mem-cache: alias to mem::getMasterPort in TLB classAndrea Mondelli
2019-03-01arch-arm: implement floating point aarch32 VCVTA familyCiro Santilli
2019-02-18arch-arm: Move GICv3 detection at startup timeGiacomo Travaglini
2019-02-13sim-se: update the arm kernel versionAyaz Akram
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
2019-02-08arch-arm: Fix Virtual interrupts in AArch64Giacomo Travaglini
2019-02-08arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30Giacomo Travaglini
2019-02-08arch-arm: Allow ArmPPI usage for PMUGiacomo Travaglini
2019-02-08arch-arm: Fix initialization of PMU countersRuben Ayrapetyan
2019-02-01cpu, arch: Replace the CCReg type with RegVal.Gabe Black
2019-01-31arch: cpu: Rename *FloatRegBits* to *FloatReg*.Gabe Black
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
2019-01-30arch-arm, configs: Create single instance of DTB autogenerationGiacomo Travaglini
2019-01-25arch-arm: Remove floatReg operand typeGiacomo Travaglini
2019-01-25arch-arm: Use VecElem instead of FloatReg for FP instructionGiacomo Travaglini
2019-01-25cpu, arch, arch-arm: Wire unused VecElem code in the O3 modelGiacomo Travaglini
2019-01-25arch-arm: Inital vector rename mode depending on A32/A64Giacomo Travaglini
2019-01-25arch-arm: Remove unused float operandsGiacomo Travaglini
2019-01-23arch-arm: Implement LoadAcquire/StoreRelease in AArch32Giacomo Travaglini
2019-01-23arch-arm: IsStoreConditional flag set depending on flavorGiacomo Travaglini
2019-01-23arch-arm: Remove SWP and SWPB instructionsGiacomo Travaglini
2019-01-23arm: Replace MiscReg with RegVal in utility.(hh|cc).Gabe Black
2019-01-22arch: cpu: Stop passing around misc registers by reference.Gabe Black
2019-01-22arm: Get rid of some register type definitions.Gabe Black
2019-01-22arch-arm: implement the GDB XML target description for ARMCiro Santilli
2019-01-22arch-arm: Move AArch32 IMPLEMENTATION DEFINED registersGiacomo Travaglini
2019-01-22sim-se: add syscalls related to pollingBrandon Potter
2019-01-16arch: Make the ISA register types aliases for the global types.Gabe Black
2019-01-16arm: Make the fp register types 64 bits.Gabe Black
2019-01-16arch-arm: Read VMPIDR instead of MPIDR when EL2 is EnabledGiacomo Travaglini
2019-01-16arch-arm: Added TLBI_ALL EL2 instructionAnouk Van Laer
2019-01-15arch-arm: Fix usage of RegId constructor for VecElemGiacomo Travaglini
2019-01-14arm: Stop using the FloatReg and FloatRegBits types.Gabe Black
2019-01-10sim-se, arch-arm: Add support for getdents64Javier Setoain
2019-01-10arch-arm, sim-se: Add support for TLS in cloneAndreas Sandberg
2019-01-10arch-arm, sim-se: Fix incorrect SP handling in cloneAndreas Sandberg
2019-01-10sim-se: Refactor clone to avoid most ifdefsAndreas Sandberg
2019-01-10arch-arm, sim-se: Wire up syscalls needed for pthreadsJavier Setoain
2019-01-10dev-arm: Add a GICv3 modelJairo Balart
generated by cgit v1.2.3 (git 2.25.1) at 2025-02-13 17:42:11 +0000