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invisispec-1.0
invisispec-with-dift
is-ift
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is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
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arm
Age
Commit message (
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Author
2019-03-20
invisispec-1.0 source
Iru Cai
2018-12-03
arch-arm: correctly set floats from GDB on aarch64
Ciro Santilli
2018-12-03
arch-arm: only change the pc address when GDB registers are set
Ciro Santilli
2018-12-03
arch-arm: fix the aarch64 GDB stub
Ciro Santilli
2018-11-28
arch-arm: Add missing template declaration
Nikos Nikoleris
2018-11-28
cpu,arch-arm: Initialise data members
Rekai Gonzalez-Alberquilla
2018-11-28
arch-arm: clang compilation fixes
Matteo Andreozzi
2018-11-27
arch, base, cpu, gpu, mem: Replace assert(0 or false with panic.
Gabe Black
2018-11-14
arch-arm: Print register name when warning on AT instructions
Giacomo Travaglini
2018-11-07
arch-arm: Deprecate usage of legacy bootloader patching
Giacomo Travaglini
2018-11-07
arch-arm: ArmSystem::resetAddr64 renamed to be used in AArch32
Giacomo Travaglini
2018-11-07
arch-arm: Implement AArch32 RVBAR
Giacomo Travaglini
2018-11-07
arch-arm: Remove SCTLR.VE bit
Giacomo Travaglini
2018-11-07
arch-arm: Refactor ISA::clear by adding a ISA::clear32 method
Giacomo Travaglini
2018-11-07
arch-arm: Remove MISCREG commented numbers
Giacomo Travaglini
2018-11-05
arch, arm: Return s1Req upon fault in s2Lookup
Anouk Van Laer
2018-11-05
arch, arm: Effect of AT instructions on descriptor handling
Anouk Van Laer
2018-10-29
syscall_emul: implement arm openat
Ciro Santilli
2018-10-29
arch-arm: FIXUP for the add PRFM PST instruction commit
Yuetsu Kodama
2018-10-26
arch-arm: We add PRFM PST instruction for arm
yuetsu.kodama
2018-10-26
arch-arm: IMPDEF for SYS instruction with CRn = {11, 15}
Giacomo Travaglini
2018-10-26
arch-arm: AArch64 Instruction for MISCREG_IMPDEF_UNIMPL
Giacomo Travaglini
2018-10-26
arch-arm: Refactor AArch64 MSR/MRS trapping
Giacomo Travaglini
2018-10-26
arch-arm: Trap to EL2 only if not in Secure State
Giacomo Travaglini
2018-10-26
arch-arm: Fix HVC trapping beahviour
Giacomo Travaglini
2018-10-26
arch-arm: CPTR_EL3.TCPAC traps EL2 accesses to CPACR_EL1
Giacomo Travaglini
2018-10-19
arm: treat aarch64 hints as NOPs instead of panic
Ciro Santilli
2018-10-19
arm: update hint instruction decoding to match ARMv8.5
Ciro Santilli
2018-10-17
arch: Get rid of the unused type AnyReg.
Gabe Black
2018-10-12
syscall_emul: update arm uname release to 3.7.0+
Ciro Santilli
2018-10-09
arch-arm: Add have_crypto System parameter
Giacomo Travaglini
2018-10-09
arch-arm: AArch64 Crypto AES
Giacomo Travaglini
2018-10-09
arch-arm: AArch64 Crypto SHA
Giacomo Travaglini
2018-10-09
arch-arm: AArch32 Crypto AES
Matt Horsnell
2018-10-09
arch-arm: AArch32 Crypto SHA
Matt Horsnell
2018-10-08
dev, arm: remove the RealViewEB platform
Ciro Santilli
2018-10-08
arch-arm: Mark ArmProcess method as override
Matteo Andreozzi
2018-10-02
sim-se: Set ArmProcess64 hwcaps depending on ID regs
Giacomo Travaglini
2018-10-02
sim-se: Different HWCAP for ArmProcess32/64
Giacomo Travaglini
2018-10-02
arch-arm: Add FP16 support introduced by Armv8.2-A
Edmund Grimley Evans
2018-10-02
arch-arm: Add FP16 support and other primitives to fplib
Edmund Grimley Evans
2018-10-01
arch-arm: Implement AArch64 ID regs as bitunions
Giacomo Travaglini
2018-10-01
arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register
Giacomo Travaglini
2018-10-01
arch-arm: Move MiscReg BitUnions into a separate header file
Giacomo Travaglini
2018-10-01
arch-arm: Init AArch64 ID registers in SE mode
Giacomo Travaglini
2018-09-28
arch-arm: raise/clear IRQ when writing to PMOVSCLR/SET
Giacomo Travaglini
2018-09-19
syscall_emul: expand AuxVector class
Brandon Potter
2018-09-13
Fix SConstruct for asan build
Earl Ou
2018-09-13
arch-arm: Correction for address size in EL1&0 translation
Anouk Van Laer
2018-09-13
arch-arm: Correction to address size in EL2/EL3
Anouk Van Laer
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