| Age | Commit message (Expand) | Author |
|---|
| 2019-10-02 | fastmodel: Let the EVS set an attribute for getSendFunctional to return. | Gabe Black |
| 2019-10-01 | fastmodel: Add a gem5Cpu attribute to the CortexA76x1. | Gabe Black |
| 2019-10-01 | fastmodel: Add a utility class which makes it easier to watch signals. | Gabe Black |
| 2019-10-01 | fastmodel: Pull out and simplify the interrupt mechanism in the GIC. | Gabe Black |
| 2019-09-27 | fastmodel: Add glue code which adapts fastmodels to run in gem5. | Gabe Black |
| 2019-09-19 | arch-arm: PSTATE.PAN changes should inval cached regs in TLB | Giacomo Travaglini |
| 2019-09-18 | arch-arm: Fix Data Abort ISS when caused by Atomic operation | Giacomo Travaglini |
| 2019-09-18 | arch-arm: ISV bit in DataAbort should check for translation stage | Giacomo Travaglini |
| 2019-09-18 | arch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2.E2H=1 | Giacomo Travaglini |
| 2019-09-06 | arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 banking | Giacomo Travaglini |
| 2019-09-06 | arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64 banking | Giacomo Travaglini |
| 2019-09-06 | arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 banking | Giacomo Travaglini |
| 2019-09-06 | arch-arm: MISCREG_ICC_BPR1_EL1 using AA64 banking | Giacomo Travaglini |
| 2019-09-06 | arch-arm: Add explicit AArch64 MiscReg banking | Giacomo Travaglini |
| 2019-09-06 | arch-arm: Use same template across all MSR inst | Giacomo Travaglini |
| 2019-09-06 | arch-arm: SySDC64 Instructions (CMO) using MiscRegIndex | Giacomo Travaglini |
| 2019-09-06 | arch-arm: fix GDB stub after SVE | Ciro Santilli |
| 2019-09-06 | arch-arm: SGI registers undecoded in AArch32 | Giacomo Travaglini |
| 2019-09-06 | arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC regs | Giacomo Travaglini |
| 2019-08-30 | arm,kvm: Fix python imports from global namespace | Giacomo Travaglini |
| 2019-08-21 | arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0 | Ciro Santilli |
| 2019-08-21 | arch-arm: Fix implicit fallthrough build errors | Chun-Chen TK Hsu |
| 2019-08-20 | arch-arm: Replace occ of opModeToEL(currOpMode/cpsr) with currEL | Giacomo Travaglini |
| 2019-08-20 | arch-arm: Replace direct use cpsr.el with currEL helper | Giacomo Travaglini |
| 2019-08-20 | arch-arm: Overload currEL helper with CPSR argument | Giacomo Travaglini |
| 2019-08-20 | arch-arm: Rewrite the currEL helper method to use opModeToEL | Giacomo Travaglini |
| 2019-08-12 | arch-arm: Added LD/ST<op> atomic instruction family and SWP instrs | Jordi Vaquero |
| 2019-08-12 | arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic func | Jordi Vaquero |
| 2019-08-07 | arch-arm: Add TypeAtomicOp class to be used by new atomic instructions | Jordi Vaquero |
| 2019-08-07 | arch-arm: adding register control flags enabling LSE implementation | Jordi Vaquero |
| 2019-08-05 | arch-arm: Implement ARMv8.1-PAN, Privileged access never | Giacomo Travaglini |
| 2019-08-05 | arch-arm: Rewrite MSR immediate instruction class | Giacomo Travaglini |
| 2019-07-27 | arch-arm: Fix reg dependency for SVE gather microops | Gabor Dozsa |
| 2019-07-27 | arch-arm: Fix tracing code for SVE gather | Gabor Dozsa |
| 2019-07-27 | arch-arm: Add SVE LD1RQ[BHWD] | Javier Setoain |
| 2019-07-27 | arch-arm: Fix decoding for SVE memory instructions | Adrià Armejach |
| 2019-07-27 | arch-arm: Add support for SVE load/store structures | Javier Setoain |
| 2019-07-19 | arch-arm: Implement ARMv8.1-HPD, Hierarchical permission disable | Giacomo Travaglini |
| 2019-07-19 | arch-arm: Add HPD bit for TCR_EL2/EL3 | Giacomo Travaglini |
| 2019-07-19 | arch-arm: Clean Fault generation when processing Long Descriptor | Giacomo Travaglini |
| 2019-07-18 | arch-arm: Add first-/non-faulting load instructions | Gabor Dozsa |
| 2019-07-17 | arch-arm: Use ExceptionLevel type in TlbEntry | Giacomo Travaglini |
| 2019-06-26 | arch, arm: Update miscRegs in getTE | Anouk Van Laer |
| 2019-06-17 | arch-arm: Move the memacc_code before op_wb in fp loads | Giacomo Travaglini |
| 2019-06-10 | arch-arm: implement VMINNM scalar thumb | Ciro Santilli |
| 2019-06-07 | arch-arm: Fix WalkerState,Descriptors default constructor | Giacomo Travaglini |
| 2019-05-31 | arm: Fix decoding of CRC32 instructions in thumb32 | Chun-Chen TK Hsu |
| 2019-05-31 | arch-arm: Treat SVE prefetch instructions as no-ops | Giacomo Gabrielli |
| 2019-05-30 | arch-arm: Add initial support for SVE gather/scatter loads/stores | Giacomo Gabrielli |
| 2019-05-30 | arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy. | Gabe Black |
