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path: root/src/arch/arm
AgeCommit message (Expand)Author
2011-02-23ARM: Set ITSTATE correctly after FlushPipeAli Saidi
2011-02-23ARM: This panic can be hit during misspeculation so it can't exist.Ali Saidi
2011-02-23ARM: Bad interworking warn way to noisy when running real code w/misspeculation.Ali Saidi
2011-02-23ARM: NEON instruction templates modified to set the predicate flag to false w...Giacomo Gabrielli
2011-02-23ARM: Squash state on FPSCR stride or len write.Ali Saidi
2011-02-23ARM: Mark store conditionals as such.Matt Horsnell
2011-02-23ARM: Do something for ISB, DSB, DMBAli Saidi
2011-02-23ARM: Fix bug that let two table walks occur in parallel.Ali Saidi
2011-02-23ARM: Make Noop actually decode to a noop and set it's instflags.Ali Saidi
2011-02-23ARM: Delete OABI syscall handling.Ali Saidi
2011-02-23ARM: Reset simulation statistics when pref counters are reset.Ali Saidi
2011-02-23ARM: Adds dummy support for a L2 latency miscreg.Ali Saidi
2011-02-11O3: Fix a few bugs in the TableWalker object.Giacomo Gabrielli
2011-02-11O3: Enhance data address translation by supporting hardware page table walkers.Giacomo Gabrielli
2011-02-03Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.Gabe Black
2011-01-18O3: Fix itstate prediction and recovery.Matt Horsnell
2011-01-18O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA.Matt Horsnell
2011-01-18ARM: The ARM decoder should not panic when decoding undefined holes is arch.Matt Horsnell
2011-01-18O3: Fixes the way prefetches are handled inside the iew unit.Matt Horsnell
2011-01-18ARM: Add support for moving predicated false dest operands from sources.Ali Saidi
2011-01-18O3: Fixes fetch deadlock when the interrupt clears before CPU handles it.Min Kyu Jeong
2011-01-18ARM: Use an actual NOP instead of a instruction that happens to do nothingAli Saidi
2011-01-18ARM: fix mismatched new/delete.Ali Saidi
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2011-01-03Make commenting on close namespace brackets consistent.Steve Reinhardt
2010-12-20Style: Replace some tabs with spaces.Gabe Black
2010-12-09ARM: Take advantage of new PCState syntax.Gabe Black
2010-12-09ARM: Get rid of some unused FP operands.Gabe Black
2010-12-07O3: Make all instructions that write a misc. register not perform the write u...Giacomo Gabrielli
2010-12-07O3: Support SWAP and predicated loads/store in ARM.Min Kyu Jeong
2010-12-07ARM: Support switchover with hardware table walkersAli Saidi
2010-11-15ARM: Add comment about the organization of the IT state registerAli Saidi
2010-11-15CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.Giacomo Gabrielli
2010-11-15ARM: Return an FailUnimp instruction when an unimplemented CP15 register is a...Ali Saidi
2010-11-15ARM: Add support for GDB on ARMWilliam Wang
2010-11-15ARM: Make utility.hh meet style guidelinesAli Saidi
2010-11-15ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.Ali Saidi
2010-11-15ARM: Add support for switching CPUsAli Saidi
2010-11-15ARM: Use the correct delete operator for RFEAli Saidi
2010-11-15ARM: Fix SRS instruction to micro-code memory operation and register update.Ali Saidi
2010-11-15ARM: Do something predictable for an UNPREDICTABLE branch.Ali Saidi
2010-11-08ARM: Add some TLB statistics for ARMAli Saidi
2010-11-08ARM: Add checkpointing supportAli Saidi
2010-11-08ARM: Add support for M5 ops in the ARM ISAAli Saidi
2010-11-08ARM: Keep the warnings to a minimum.Ali Saidi
2010-11-08ARM: Don't return the result of a table walk the same cycle it's completed.Ali Saidi
2010-11-08ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.Ali Saidi
2010-11-08ARM: Make all ARM uops delayed commit.Ali Saidi
2010-11-08sim: Use forward declarations for ports.Ali Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black