| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2010-08-31 | ARM: Get rid of the checkFpEnableFault function in ARM. | Gabe Black | |
| 2010-08-25 | ARM: Support unaligned memory access. | Min Kyu Jeong | |
| Without this flag set, page-crossing requests were not split into two mem request. Depending on the alignment bit in the SCTLR, misaligned access could raise a fault. However it seems unnecessary to implement that. | |||
| 2010-08-25 | ARM: Seperate the queues of L1 and L2 walker states. | Gene WU | |
| 2010-08-25 | ARM: Adding a bogus fault that does nothing. | Min Kyu Jeong | |
| This fault can used to flush the pipe, not including the faulting instruction. The particular case I needed this was for a self-modifying code. It needed to drain the store queue and force the following instruction to refetch from icache. DCCMVAC cp15 mcr instruction is modified to raise this fault. | |||
| 2010-08-25 | ARM: Remove ALPHA KSeg functions. | William Wang | |
| These were erronously copied years ago into the ARM directory. | |||
| 2010-08-25 | ARM: Limited implementation of dprintk. | Ali Saidi | |
| Does not work with vfp arguments or arguments passed on the stack. | |||
| 2010-08-25 | ARM: Fixed register flattening logic (FP_Base_DepTag was set too low) | Min Kyu Jeong | |
| When decoding a srs instruction, invalid mode encoding returns invalid instruction. This can happen when garbage instructions are fetched from mispredicted path | |||
| 2010-08-25 | ARM: Make VMSR, RFE PC/LR etc non speculative, and serializing | Ali Saidi | |
| 2010-08-25 | ARM: Use fewer micro-ops for register update loads if possible. | Gene WU | |
| Allow some loads that update the base register to use just two micro-ops. three micro-ops are only used if the destination register matches the offset register or the PC is the destination regsiter. If the PC is updated it needs to be the last micro-op otherwise O3 will mispredict. | |||
| 2010-08-25 | ARM: Set the high bits in the part number so it's considered new by some code. | Ali Saidi | |
| 2010-08-25 | ARM: Fix VFP enabled checks for mem instructions | Ali Saidi | |
| 2010-08-25 | ARM: Seperate out the renamable bits in the FPSCR. | Gabe Black | |
| 2010-08-25 | ARM: Eliminate some unused enums. | Gabe Black | |
| 2010-08-25 | ARM: Fix type comparison warnings in Neon. | Gabe Black | |
| 2010-08-25 | ARM: Implement CPACR register and return Undefined Instruction when FP ↵ | Gabe Black | |
| access is disabled. | |||
| 2010-08-25 | ARM: Implement all ARM SIMD instructions. | Gabe Black | |
| 2010-08-25 | ARM: Expand the mode checking utility functions. | Gabe Black | |
| inUserMode now can take either a threadcontext or a CPSR value directly. If given a thread context it just extracts the CPSR and calls the other version. An inPrivelegedMode function was also implemented which just returns the opposite of inUserMode. | |||
| 2010-08-23 | ISA: Get rid of old, unused utility functions cluttering up the ISAs. | Gabe Black | |
| 2010-08-23 | ARM: Improve printing of uop disassembly. | Min Kyu Jeong | |
| 2010-08-23 | ARM: Clean up flattening for SPSR adding | Min Kyu Jeong | |
| 2010-08-23 | ARM: Implement DBG instruction that doesn't do much for now. | Gene Wu | |
| 2010-08-23 | MEM: Make CLREX a first class request operation and clear locks in caches ↵ | Gene Wu | |
| when it in received | |||
| 2010-08-23 | ARM: Make sure that software prefetch instructions can't change the state of ↵ | Gene Wu | |
| the TLB | |||
| 2010-08-23 | ARM: Don't write tracedata on writes, it might have been freed already. | Gene Wu | |
| 2010-08-23 | ARM: Implement CLREX init/complete acc methods | Gene Wu | |
| 2010-08-23 | ARM: Fix Uncachable TLB requests and decoding of xn bit | Gene Wu | |
| 2010-08-23 | ARM: For non-cachable accesses set the UNCACHABLE flag | Gene Wu | |
| 2010-08-23 | ARM: Implement DSB, DMB, ISB | Gene Wu | |
| 2010-08-23 | ARM: Get SCTLR TE bit from reset SCTLR | Gene Wu | |
| 2010-08-23 | ARM: Implement CLREX | Gene Wu | |
| 2010-08-23 | ARM: BX instruction can be contitional if last instruction in a IT block | Gene Wu | |
| Branches are allowed to be the last instuction in an IT block. Before it was assumed that they could not. So Branches in thumb2 were Uncond. | |||
| 2010-08-23 | ARM: mark msr/mrs instructions as SerializeBefore/After | Min Kyu Jeong | |
| Since miscellaneous registers bypass wakeup logic, force serialization to resolve data dependencies through them * * * ARM: adding non-speculative/serialize flags for instructions change CPSR | |||
| 2010-08-23 | ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate. | Min Kyu Jeong | |
| THis allows the CPU to handle predicated-false instructions accordingly. This particular patch makes loads that are predicated-false to be sent straight to the commit stage directly, not waiting for return of the data that was never requested since it was predicated-false. | |||
| 2010-08-23 | ARM: adding genMachineCheckFault() stub for ARM that doesn't panic | Min Kyu Jeong | |
| 2010-08-23 | ARM: DFSR status value for sync external data abort is expected to be 0x8 in ↵ | Gene Wu | |
| ARMv7 | |||
| 2010-08-23 | ARM: Temporary local variables can't conflict with isa parser operands. | Gene Wu | |
| PC is an operand, so we can't have a temp called PC | |||
| 2010-08-23 | ARM: Exclusive accesses must be double word aligned | Ali Saidi | |
| 2010-08-23 | ARM: Add some registers for big loads/stores to support neon. | Ali Saidi | |
| 2010-08-23 | ARM: Decode neon memory instructions. | Ali Saidi | |
| 2010-08-23 | ARM: Clean up the ISA desc portion of the ARM memory instructions. | Gabe Black | |
| 2010-08-23 | ARM: We don't currently support ThumbEE exceptions, so don't report that we do | Ali Saidi | |
| 2010-08-23 | ARM: Add system for ARM/Linux and bootstrapping | Ali Saidi | |
| 2010-08-23 | ARM: Implement some more misc registers | Ali Saidi | |
| 2010-08-23 | ARM: Fix an un-initialized variable bug | Ali Saidi | |
| 2010-08-23 | Loader: Make the load address mask be a parameter of the system rather than ↵ | Ali Saidi | |
| a constant. This allows one two different OS requirements for the same ISA to be handled. Some OSes are compiled for a virtual address and need to be loaded into physical memory that starts at address 0, while other bare metal tools generate images that start at address 0. | |||
| 2010-08-23 | ARM: Finish the timing translation when taking a fault. | Min Kyu Jeong | |
| 2010-08-23 | ARM: Use a stl queue for the table walker state | Dam Sunwoo | |
| 2010-08-23 | Compiler: Fixes for GCC 4.5. | Ali Saidi | |
| 2010-08-17 | sim: revamp unserialization procedure | Steve Reinhardt | |
| Replace direct call to unserialize() on each SimObject with a pair of calls for better control over initialization in both ckpt and non-ckpt cases. If restoring from a checkpoint, loadState(ckpt) is called on each SimObject. The default implementation simply calls unserialize() if there is a corresponding checkpoint section, so we get backward compatibility for existing objects. However, objects can override loadState() to get other behaviors, e.g., doing other programmed initializations after unserialize(), or complaining if no checkpoint section is found. (Note that the default warning for a missing checkpoint section is now gone.) If not restoring from a checkpoint, we call the new initState() method on each SimObject instead. This provides a hook for state initializations that are only required when *not* restoring from a checkpoint. Given this new framework, do some cleanup of LiveProcess subclasses and X86System, which were (in some cases) emulating initState() behavior in startup via a local flag or (in other cases) erroneously doing initializations in startup() that clobbered state loaded earlier by unserialize(). | |||
| 2010-07-15 | ARM: Make an SRS instruction with a bad mode cause an undefined instruction ↵ | Gabe Black | |
| fault. | |||
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