| Age | Commit message (Expand) | Author |
|---|
| 2017-03-03 | arm, kvm: enable running 32-bit Guest under ARM KVM64 | Rahul Thakur |
| 2017-03-03 | arm, kvm: fix saving/restoring conditional flags in ARM KVM64 | Rahul Thakur |
| 2017-02-27 | syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess s... | Brandon Potter |
| 2015-07-20 | syscall_emul: [patch 13/22] add system call retry capability | Brandon Potter |
| 2017-02-21 | arm: Fix DPRINTFs with arguments in the instruction declarations | Nikos Nikoleris |
| 2017-02-21 | arm: Blame the right instruction address on a Prefetch Abort | Nikos Nikoleris |
| 2016-11-09 | syscall_emul: [patch 8/22] refactor process class | Brandon Potter |
| 2016-11-09 | syscall_emul: [patch 5/22] remove LiveProcess class and use Process instead | Brandon Potter |
| 2017-02-14 | arm, kvm: remove KvmGic | Curtis Dunham |
| 2017-02-14 | arm, kvm: implement MuxingKvmGic | Curtis Dunham |
| 2017-02-14 | sim, kvm: make KvmVM a System parameter | Curtis Dunham |
| 2017-02-14 | sim,kvm,arm: fix typos | Curtis Dunham |
| 2017-02-09 | arm: AArch64 report cache size correctly when reading CTR_EL0 | Bjoern A. Zeeb |
| 2016-11-09 | style: [patch 3/22] reduce include dependencies in some headers | Brandon Potter |
| 2016-11-09 | syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc | Brandon Potter |
| 2016-11-09 | style: [patch 1/22] use /r/3648/ to reorganize includes | Brandon Potter |
| 2017-01-03 | sim: Remove redundant export_method_cxx_predecls | Andreas Sandberg |
| 2016-12-19 | arm: provide correct timer availability in ID_PFR1 register | Curtis Dunham |
| 2016-12-19 | arm: compute ID_AA64PFR{0,1}_EL1 registers | Curtis Dunham |
| 2016-12-19 | arm: compute ID_PFR{0,1} registers | Curtis Dunham |
| 2016-12-19 | arm: miscreg refactoring | Curtis Dunham |
| 2016-12-19 | arm: audit SCTLR | Curtis Dunham |
| 2016-12-19 | arm: remove SCTLR.FI | Curtis Dunham |
| 2016-12-19 | arm: update AArch{64,32} register mappings | Curtis Dunham |
| 2016-10-15 | cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClass | Fernando Endo |
| 2016-10-13 | isa,arm: Add missing AArch32 FP instructions | Mitch Hayenga |
| 2016-09-15 | arm: Add m5_fail support for aarch64 | Ricardo Alves |
| 2016-08-15 | cpu, arch: fix the type used for the request flags | Nikos Nikoleris |
| 2016-08-02 | arm: refactor page table walking | Curtis Dunham |
| 2016-08-02 | arm: warn not fail on use of missing miscreg CNTHCTL_EL2 | Dylan Johnson |
| 2016-08-02 | arm: Check TLB stage 2 permissions in AArch64 | Dylan Johnson |
| 2016-08-02 | arm: correctly assign faulting IPA's to HPFAR_EL2 | Dylan Johnson |
| 2016-08-02 | arm: Add TLBI instruction for stage 2 IPA's | Dylan Johnson |
| 2016-08-02 | arm: Fix stage 2 memory attribute checking in AArch64 | Dylan Johnson |
| 2016-08-02 | arm: Fix trapping to Hypervisor during MSR/MRS read/write | Dylan Johnson |
| 2016-08-02 | arm: Fix secure state checking in various places | Dylan Johnson |
| 2016-08-02 | arm: Fix stage 2 determination in table walker | Dylan Johnson |
| 2016-08-02 | arm: Refactor aarch64 table walk logic to remove redundancy | Dylan Johnson |
| 2016-08-02 | arm: Add check to fault routing for hypervisor/virtualization | Dylan Johnson |
| 2016-08-02 | arm: Fix EL perceived at TLB for address translation instructions | Dylan Johnson |
| 2016-08-02 | arm: Add AArch64 hypervisor call instruction 'hvc' | Dylan Johnson |
| 2016-08-02 | arm: add stage2 translation support | Dylan Johnson |
| 2016-08-02 | arm: enable EL2 support | Curtis Dunham |
| 2016-08-02 | arm: invalidate TLB miscreg cache on modification of HSCTLR | Dylan Johnson |
| 2016-08-02 | arm: change instruction classes to catch hyp traps | Dylan Johnson |
| 2016-07-21 | isa: Modify get/check interrupt routines | Mitch Hayenga |
| 2016-07-11 | arm: Don't consult the TLB test iface for functional translations | Andreas Sandberg |
| 2016-06-20 | arm: Mark uninitialized new TLB entries as not valid | Nikos Nikoleris |
| 2016-06-20 | kern, arm: Dump dmesg on kernel panic/oops | Andreas Sandberg |
| 2016-06-06 | sim: Call regStats of base-class as well | Stephan Diestelhorst |
