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path: root/src/arch/arm
AgeCommit message (Expand)Author
2017-02-21arm: Fix DPRINTFs with arguments in the instruction declarationsNikos Nikoleris
2017-02-21arm: Blame the right instruction address on a Prefetch AbortNikos Nikoleris
2016-11-09syscall_emul: [patch 8/22] refactor process classBrandon Potter
2016-11-09syscall_emul: [patch 5/22] remove LiveProcess class and use Process insteadBrandon Potter
2017-02-14arm, kvm: remove KvmGicCurtis Dunham
2017-02-14arm, kvm: implement MuxingKvmGicCurtis Dunham
2017-02-14sim, kvm: make KvmVM a System parameterCurtis Dunham
2017-02-14sim,kvm,arm: fix typosCurtis Dunham
2017-02-09arm: AArch64 report cache size correctly when reading CTR_EL0Bjoern A. Zeeb
2016-11-09style: [patch 3/22] reduce include dependencies in some headersBrandon Potter
2016-11-09syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .ccBrandon Potter
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2017-01-03sim: Remove redundant export_method_cxx_predeclsAndreas Sandberg
2016-12-19arm: provide correct timer availability in ID_PFR1 registerCurtis Dunham
2016-12-19arm: compute ID_AA64PFR{0,1}_EL1 registersCurtis Dunham
2016-12-19arm: compute ID_PFR{0,1} registersCurtis Dunham
2016-12-19arm: miscreg refactoringCurtis Dunham
2016-12-19arm: audit SCTLRCurtis Dunham
2016-12-19arm: remove SCTLR.FICurtis Dunham
2016-12-19arm: update AArch{64,32} register mappingsCurtis Dunham
2016-10-15cpu, arm: Distinguish Float* and SimdFloat*, create FloatMem* opClassFernando Endo
2016-10-13isa,arm: Add missing AArch32 FP instructionsMitch Hayenga
2016-09-15arm: Add m5_fail support for aarch64Ricardo Alves
2016-08-15cpu, arch: fix the type used for the request flagsNikos Nikoleris
2016-08-02arm: refactor page table walkingCurtis Dunham
2016-08-02arm: warn not fail on use of missing miscreg CNTHCTL_EL2Dylan Johnson
2016-08-02arm: Check TLB stage 2 permissions in AArch64Dylan Johnson
2016-08-02arm: correctly assign faulting IPA's to HPFAR_EL2Dylan Johnson
2016-08-02arm: Add TLBI instruction for stage 2 IPA'sDylan Johnson
2016-08-02arm: Fix stage 2 memory attribute checking in AArch64Dylan Johnson
2016-08-02arm: Fix trapping to Hypervisor during MSR/MRS read/writeDylan Johnson
2016-08-02arm: Fix secure state checking in various placesDylan Johnson
2016-08-02arm: Fix stage 2 determination in table walkerDylan Johnson
2016-08-02arm: Refactor aarch64 table walk logic to remove redundancyDylan Johnson
2016-08-02arm: Add check to fault routing for hypervisor/virtualizationDylan Johnson
2016-08-02arm: Fix EL perceived at TLB for address translation instructionsDylan Johnson
2016-08-02arm: Add AArch64 hypervisor call instruction 'hvc'Dylan Johnson
2016-08-02arm: add stage2 translation supportDylan Johnson
2016-08-02arm: enable EL2 supportCurtis Dunham
2016-08-02arm: invalidate TLB miscreg cache on modification of HSCTLRDylan Johnson
2016-08-02arm: change instruction classes to catch hyp trapsDylan Johnson
2016-07-21isa: Modify get/check interrupt routinesMitch Hayenga
2016-07-11arm: Don't consult the TLB test iface for functional translationsAndreas Sandberg
2016-06-20arm: Mark uninitialized new TLB entries as not validNikos Nikoleris
2016-06-20kern, arm: Dump dmesg on kernel panic/oopsAndreas Sandberg
2016-06-06sim: Call regStats of base-class as wellStephan Diestelhorst
2016-06-02arm: refactor page table format determinationCurtis Dunham
2016-06-02arm: Rewrite ERET to behave according to the ARMv8 ARMAndreas Sandberg
2016-06-02arm: Correctly check FP/SIMD access permission in aarch32Andreas Sandberg
2016-05-31arm: Enable LPAE support by defaultAndreas Sandberg