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AgeCommit message (Expand)Author
2018-02-07arch-arm: Change function name for banked miscregsGiacomo Travaglini
2018-02-07arch-arm: Fix AArch32 SETEND InstructionGiacomo Travaglini
2018-02-07arch-arm: Correct Illegal Exception Return detectionGiacomo Travaglini
2018-02-07arch-arm: ELUsingAArch32K from armarm pseudocodeGiacomo Travaglini
2018-02-07arch-arm: isSecureBelow from armarm pseudocodeGiacomo Travaglini
2018-02-07arch-arm: Fix incorrect assumptions in ELIs64Chuan Zhu
2018-02-05arch-arm: Removing Serializing flag from ISBGiacomo Travaglini
2018-01-29arch-arm: understandably initialize register permissionsCurtis Dunham
2018-01-29arm: extend MiscReg metadata structuresCurtis Dunham
2018-01-29arch-arm: understandably initialize register mappingsCurtis Dunham
2018-01-29arm: DT autogeneration - Generate memory nodeGlenn Bergmans
2018-01-29arm: DT autogeneration - Device Tree generation methodsGlenn Bergmans
2018-01-20arch, mem: Make the page table lookup function return a pointer.Gabe Black
2018-01-20arm, base: Generalize and move the BitUnion hash struct.Gabe Black
2018-01-20base: Rework bitunions so they can be more flexible.Gabe Black
2018-01-20sim, arch, base: Refactor the base remote GDB class.Gabe Black
2018-01-19arch, mem, sim: Consolidate and rename the SE mode page table classes.Gabe Black
2018-01-15arch: Fix a fatal_if in most of the arch's process classes.Gabe Black
2018-01-11arm, power: Make the python TLB simobjects inherit from BaseTLB.Gabe Black
2018-01-11arch,mem: Remove the default value for page size.Gabe Black
2018-01-11arch,mem: Move page table construction into the arch classes.Gabe Black
2018-01-10style: change C/C++ source permissions to noexecBKP
2018-01-10alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT.Gabe Black
2018-01-09arm: Make translateFunctional override the base implementation.Gabe Black
2017-12-23alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst.Gabe Black
2017-12-22arch,cpu: "virtualize" the TLB interface.Gabe Black
2017-12-21arch-arm: Fixed WFE/WFI trapping behaviourGiacomo Travaglini
2017-12-21arch-arm: Hyp routed undef fault need to change its syndromeGiacomo Travaglini
2017-12-21arch-arm: Fix StaticInst encoding() methodGiacomo Travaglini
2017-12-19arch-arm: Instruction size methods in StaticInst classGiacomo Travaglini
2017-12-19arch-arm: Change casting type from reinterpret to staticGiacomo Travaglini
2017-12-14misc: Updates for gcc7.2 for x86Jason Lowe-Power
2017-12-13arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.Gabe Black
2017-12-08arm: Change access permission in TPIDRURO and TPIDRURWGiacomo Travaglini
2017-12-05arm: Add support for the dc {civac, cvac, cvau, ivac} instrNikos Nikoleris
2017-12-05arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructionsNikos Nikoleris
2017-12-05arm: Add CMO support for Non-Cacheable memoryNikos Nikoleris
2017-12-04misc: Rename misc.(hh|cc) to logging.(hh|cc)Gabe Black
2017-12-01arm: Enable ns registers access in secure modeGiacomo Travaglini
2017-11-28arch-arm: Add haveEL pseudocode functionGiacomo Travaglini
2017-11-28arch-arm: Add assertions when extracting an ArmSystem from a TCGiacomo Travaglini
2017-11-22arch-arm: Add support for the brk instructionAndreas Sandberg
2017-11-22arch-arm: HVC instruction undefined in secure EL1Giacomo Travaglini
2017-11-21arch-arm: ArmPMU refactorJose Marinho
2017-11-21arch-arm: Do not increment PMU cycle event in WFI/WFEJose Marinho
2017-11-21arch-arm: Fix MCR/MRC disassembleGiacomo Travaglini
2017-11-21arch-arm: Fix MSR/MRS disassembleGiacomo Travaglini
2017-11-20arch-arm: Ensure counters keep events on checkpoint resumeJose Marinho
2017-11-17sim: Implement load_addr_mask auto-calculationGeoffrey Blake
2017-11-16arch, arm: Print value being ignored on DummyISA writeSean McGoogan