gem5 - gem5

Age	Commit message (Expand)	Author
2012-01-09	ARM: Add support for initparam m5 op	Ali Saidi
2011-12-13	gcc: fix unused variable warnings from GCC 4.6.1	Nathan Binkert
2011-12-01	Device: Make changes necessary to support a coherent page walker cache.	Mitchell Hayenga
2011-12-01	ARM: Add IsSerializeAfter and IsNonSpeculative flag to the syscall instruction .	Ali Saidi
2011-10-31	GCC: Get everything working with gcc 4.6.1.	Gabe Black
2011-10-22	SE: move page allocation from PageTable to Process	Steve Reinhardt
2011-10-22	syscall_emul: implement MAP_FIXED option to mmap()	Steve Reinhardt
2011-09-27	Faults: Replace calls to genMachineCheckFault with M5PanicFault.	Gabe Black
2011-09-26	ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.	Gabe Black
2011-09-19	PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts.	Gabe Black
2011-09-18	Pseudoinst: Add an initParam pseudo inst function.	Gabe Black
2011-09-13	ARM: update TLB to set request packet ASID field	Daniel Johnson
2011-09-13	CP15 c15: enable execution with accesses to c15 registers	Chander Sudanthi
2011-09-13	ARM: Implement numcpus bits in L2CTLR register.	Daniel Johnson
2011-09-13	LSQ: Only trigger a memory violation with a load/load if the value changes.	Ali Saidi
2011-09-09	StaticInst: Merge StaticInst and StaticInstBase.	Gabe Black
2011-09-09	Decode: Pull instruction decoding out of the StaticInst class into its own.	Gabe Black
2011-08-19	ARM: Mark some variables uncacheable until boot all CPUs are enabled.	Ali Saidi
2011-08-19	ARM: Add VExpress_E support with PCIe to gem5	Ali Saidi
2011-08-19	ARM: Add support for Versatile Express boards	Ali Saidi
2011-08-19	ARM: Add support for DIV/SDIV instructions.	Ali Saidi
2011-08-19	Fix bugs due to interaction between SEV instructions and O3 pipeline	Geoffrey Blake
2011-08-19	ARM: Fix a memory leak with the table walker.	Ali Saidi
2011-07-15	ARM: Fix SWP/SWPB undefined instruction behavior	Wade Walker
2011-07-15	ARM: Add two unimplemented miscellaneous registers.	Wade Walker
2011-07-05	ISA parser: Define operand types with a ctype directly.	Gabe Black
2011-07-02	ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.	Gabe Black
2011-07-02	ISA: Use readBytes/writeBytes for all instruction level memory operations.	Gabe Black
2011-06-19	cpus/isa: add a != operator for pcstate	Korey Sewell
2011-06-17	ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.	Gedare Bloom
2011-06-16	ARM: Handle case where new TLB size is different from previous TLB size.	Ali Saidi
2011-06-16	ARM: Fix memset on TLB flush and initialization	Chander Sudanthi
2011-06-02	scons: rename TraceFlags to DebugFlags	Nathan Binkert
2011-06-02	copyright: clean up copyright blocks	Nathan Binkert
2011-05-23	O3: Fix issue with interrupts/faults occuring in the middle of a macro-op	Geoffrey Blake
2011-05-18	gcc: fix an uninitialized variable warning from G++ 4.5	Nathan Binkert
2011-05-13	ARM: Generate condition code setting code based on which codes are set.	Ali Saidi
2011-05-13	ARM: Construct the predicate test register for more instruction programatically.	Ali Saidi
2011-05-13	ARM: Further break up condition code into NZ, C, V bits.	Ali Saidi
2011-05-13	ARM: Remove the saturating (Q) condition code from the renamed register.	Ali Saidi
2011-05-13	ARM: Break up condition codes into normal flags, saturation, and simd.	Ali Saidi
2011-05-13	Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.	Chander Sudanthi
2011-05-13	ARM: Better RealView/Versatile EB platform support.	Chander Sudanthi
2011-05-04	ARM: Add support for loading the a bootloader and configuring parameters for it	Ali Saidi
2011-05-04	ARM: Implement WFE/WFI/SEV semantics.	Prakash Ramrakhyani
2011-05-04	ARM: Add support for MP misc regs and broadcast flushes.	Ali Saidi
2011-05-04	ARM: Add vfpv3 support to native trace.	Ali Saidi
2011-05-04	ARM: Fix small bug with vcvt instruction	Ali Saidi
2011-04-20	fix some build problems from prior changesets	Nathan Binkert
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert