gem5 - gem5

Age	Commit message (Expand)	Author
2011-02-23	ARM: Set ITSTATE correctly after FlushPipe	Ali Saidi
2011-02-23	ARM: This panic can be hit during misspeculation so it can't exist.	Ali Saidi
2011-02-23	ARM: Bad interworking warn way to noisy when running real code w/misspeculation.	Ali Saidi
2011-02-23	ARM: NEON instruction templates modified to set the predicate flag to false w...	Giacomo Gabrielli
2011-02-23	ARM: Squash state on FPSCR stride or len write.	Ali Saidi
2011-02-23	ARM: Mark store conditionals as such.	Matt Horsnell
2011-02-23	ARM: Do something for ISB, DSB, DMB	Ali Saidi
2011-02-23	ARM: Fix bug that let two table walks occur in parallel.	Ali Saidi
2011-02-23	ARM: Make Noop actually decode to a noop and set it's instflags.	Ali Saidi
2011-02-23	ARM: Delete OABI syscall handling.	Ali Saidi
2011-02-23	ARM: Reset simulation statistics when pref counters are reset.	Ali Saidi
2011-02-23	ARM: Adds dummy support for a L2 latency miscreg.	Ali Saidi
2011-02-11	O3: Fix a few bugs in the TableWalker object.	Giacomo Gabrielli
2011-02-11	O3: Enhance data address translation by supporting hardware page table walkers.	Giacomo Gabrielli
2011-02-03	Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.	Gabe Black
2011-01-18	O3: Fix itstate prediction and recovery.	Matt Horsnell
2011-01-18	O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA.	Matt Horsnell
2011-01-18	ARM: The ARM decoder should not panic when decoding undefined holes is arch.	Matt Horsnell
2011-01-18	O3: Fixes the way prefetches are handled inside the iew unit.	Matt Horsnell
2011-01-18	ARM: Add support for moving predicated false dest operands from sources.	Ali Saidi
2011-01-18	O3: Fixes fetch deadlock when the interrupt clears before CPU handles it.	Min Kyu Jeong
2011-01-18	ARM: Use an actual NOP instead of a instruction that happens to do nothing	Ali Saidi
2011-01-18	ARM: fix mismatched new/delete.	Ali Saidi
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
2011-01-03	Make commenting on close namespace brackets consistent.	Steve Reinhardt
2010-12-20	Style: Replace some tabs with spaces.	Gabe Black
2010-12-09	ARM: Take advantage of new PCState syntax.	Gabe Black
2010-12-09	ARM: Get rid of some unused FP operands.	Gabe Black
2010-12-07	O3: Make all instructions that write a misc. register not perform the write u...	Giacomo Gabrielli
2010-12-07	O3: Support SWAP and predicated loads/store in ARM.	Min Kyu Jeong
2010-12-07	ARM: Support switchover with hardware table walkers	Ali Saidi
2010-11-15	ARM: Add comment about the organization of the IT state register	Ali Saidi
2010-11-15	CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.	Giacomo Gabrielli
2010-11-15	ARM: Return an FailUnimp instruction when an unimplemented CP15 register is a...	Ali Saidi
2010-11-15	ARM: Add support for GDB on ARM	William Wang
2010-11-15	ARM: Make utility.hh meet style guidelines	Ali Saidi
2010-11-15	ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.	Ali Saidi
2010-11-15	ARM: Add support for switching CPUs	Ali Saidi
2010-11-15	ARM: Use the correct delete operator for RFE	Ali Saidi
2010-11-15	ARM: Fix SRS instruction to micro-code memory operation and register update.	Ali Saidi
2010-11-15	ARM: Do something predictable for an UNPREDICTABLE branch.	Ali Saidi
2010-11-08	ARM: Add some TLB statistics for ARM	Ali Saidi
2010-11-08	ARM: Add checkpointing support	Ali Saidi
2010-11-08	ARM: Add support for M5 ops in the ARM ISA	Ali Saidi
2010-11-08	ARM: Keep the warnings to a minimum.	Ali Saidi
2010-11-08	ARM: Don't return the result of a table walk the same cycle it's completed.	Ali Saidi
2010-11-08	ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.	Ali Saidi
2010-11-08	ARM: Make all ARM uops delayed commit.	Ali Saidi
2010-11-08	sim: Use forward declarations for ports.	Ali Saidi
2010-10-31	ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.	Gabe Black