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path: root/src/arch/arm
AgeCommit message (Expand)Author
2011-03-26mips: cleanup ISA-specific codeKorey Sewell
2011-03-25Arm: Add in a missing miscRegName.Gabe Black
2011-03-24Arm: Get rid of unused and incomplete setCp15Register and readCp15Register.Gabe Black
2011-03-24Arm: Get rid of the unused copyStringArray32 method from Arm process classes.Gabe Black
2011-03-17ARM: Add minimal ARM_SE support for m5threads.Chris Emmons
2011-03-17ARM: Fix subtle bug in LDM.Ali Saidi
2011-03-17ARM: Implement the Instruction Set Attribute Registers (ISAR).Ali Saidi
2011-03-17ARM: Identify branches as conditional or unconditional and direct or indirect.Ali Saidi
2011-03-17ARM: Fix small bug with VLDM/VSTM instructions.Ali Saidi
2011-03-17ARM: Detect and skip udelay() functions in linux kernel.Ali Saidi
2011-03-17ARM: Allow conditional quiesce instructions.Ali Saidi
2011-03-17ARM: Fix RFE macrop.Matt Horsnell
2011-03-17ARM: Rename registers used as temporary state by microops.Matt Horsnell
2011-03-17O3: Send instruction back to fetch on squash to seed predecoder correctly.Ali Saidi
2011-03-17ARM: Previous change didn't end up setting instFlags, this does.Ali Saidi
2011-03-01Spelling: Fix the a spelling error by changing mmaped to mmapped.Gabe Black
2011-02-23ARM: Set ITSTATE correctly after FlushPipeAli Saidi
2011-02-23ARM: This panic can be hit during misspeculation so it can't exist.Ali Saidi
2011-02-23ARM: Bad interworking warn way to noisy when running real code w/misspeculation.Ali Saidi
2011-02-23ARM: NEON instruction templates modified to set the predicate flag to false w...Giacomo Gabrielli
2011-02-23ARM: Squash state on FPSCR stride or len write.Ali Saidi
2011-02-23ARM: Mark store conditionals as such.Matt Horsnell
2011-02-23ARM: Do something for ISB, DSB, DMBAli Saidi
2011-02-23ARM: Fix bug that let two table walks occur in parallel.Ali Saidi
2011-02-23ARM: Make Noop actually decode to a noop and set it's instflags.Ali Saidi
2011-02-23ARM: Delete OABI syscall handling.Ali Saidi
2011-02-23ARM: Reset simulation statistics when pref counters are reset.Ali Saidi
2011-02-23ARM: Adds dummy support for a L2 latency miscreg.Ali Saidi
2011-02-11O3: Fix a few bugs in the TableWalker object.Giacomo Gabrielli
2011-02-11O3: Enhance data address translation by supporting hardware page table walkers.Giacomo Gabrielli
2011-02-03Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.Gabe Black
2011-01-18O3: Fix itstate prediction and recovery.Matt Horsnell
2011-01-18O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA.Matt Horsnell
2011-01-18ARM: The ARM decoder should not panic when decoding undefined holes is arch.Matt Horsnell
2011-01-18O3: Fixes the way prefetches are handled inside the iew unit.Matt Horsnell
2011-01-18ARM: Add support for moving predicated false dest operands from sources.Ali Saidi
2011-01-18O3: Fixes fetch deadlock when the interrupt clears before CPU handles it.Min Kyu Jeong
2011-01-18ARM: Use an actual NOP instead of a instruction that happens to do nothingAli Saidi
2011-01-18ARM: fix mismatched new/delete.Ali Saidi
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2011-01-03Make commenting on close namespace brackets consistent.Steve Reinhardt
2010-12-20Style: Replace some tabs with spaces.Gabe Black
2010-12-09ARM: Take advantage of new PCState syntax.Gabe Black
2010-12-09ARM: Get rid of some unused FP operands.Gabe Black
2010-12-07O3: Make all instructions that write a misc. register not perform the write u...Giacomo Gabrielli
2010-12-07O3: Support SWAP and predicated loads/store in ARM.Min Kyu Jeong
2010-12-07ARM: Support switchover with hardware table walkersAli Saidi
2010-11-15ARM: Add comment about the organization of the IT state registerAli Saidi
2010-11-15CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.Giacomo Gabrielli
2010-11-15ARM: Return an FailUnimp instruction when an unimplemented CP15 register is a...Ali Saidi