gem5 - gem5

Age	Commit message (Expand)	Author
2010-06-02	ARM: Flesh out the 32 bit thumb store single instructions.	Gabe Black
2010-06-02	ARM: Implement the 32 bit thumb load word instructions.	Gabe Black
2010-06-02	ARM: Add an operand for accessing the current PC.	Gabe Black
2010-06-02	ARM: Flesh out 32 bit thumb load word decoding.	Gabe Black
2010-06-02	ARM: Implement some 32 bit thumb data processing immediate instructions.	Gabe Black
2010-06-02	ARM: Replace the "never" condition with the "unconditional" condition.	Gabe Black
2010-06-02	ARM: Add a base class for 32 bit thumb data processing immediate instructions.	Gabe Black
2010-06-02	ARM: Add a function to decode 32 bit thumb immediate values.	Gabe Black
2010-06-02	ARM: Expand the decoding for 32 bit thumb data processing immediate instructi...	Gabe Black
2010-06-02	ARM: Stub out the 32 bit Thumb portion of the decoder.	Gabe Black
2010-06-02	ARM: Add bitfields for 32 bit thumb.	Gabe Black
2010-06-02	ARM: Decode VFP instructions.	Gabe Black
2010-06-02	ARM: Stub out the 16 bit thumb decoder.	Gabe Black
2010-06-02	ARM: Add thumb bitfields to the ExtMachInst and the isa definition.	Gabe Black
2010-06-02	ARM: Make the decoder handle thumb instructions separately.	Gabe Black
2010-06-02	ARM: Add a thumb bit bitfield.	Gabe Black
2010-06-02	ARM: Make the predecoder handle Thumb instructions.	Gabe Black
2010-06-02	ARM: Make sure ExtMachInst is used consistently instead of regular MachInst.	Gabe Black
2010-06-02	ARM: Add a bitfield for setting the regular, inst bits of an ExtMachInst.	Gabe Black
2010-06-02	ARM: Add a bit to the ExtMachInst to select thumb mode.	Gabe Black
2010-06-02	ARM: Allow ARM processes to start in Thumb mode.	Gabe Black
2010-06-02	ARM: Add a new base class for instructions that can do an interworking branch.	Gabe Black
2010-06-02	ARM: Track the current ISA mode using the PC.	Gabe Black
2010-06-02	ARM: Remove IsControl from operands that don't imply control transfers.	Gabe Black
2010-03-23	cpu: fix exec tracing memory corruption bug	Steve Reinhardt
2010-02-12	O3PCU: Split loads and stores that cross cache line boundaries.	Timothy M. Jones
2009-11-17	ARM: Begin implementing CP15	Ali Saidi
2009-11-17	ARM: Differentiate between LDM exception return and LDM user regs.	Ali Saidi
2009-11-17	ARM: Boilerplate full-system code.	Ali Saidi
2009-11-16	imported patch isa_fixes2.diff	Ali Saidi
2009-11-15	ARM: Make the exception return form of ldm restore CPSR.	Gabe Black
2009-11-15	ARM: Create a new type of load uop that restores spsr into cpsr.	Gabe Black
2009-11-14	ARM: Check in the actual change from the last commit.	Gabe Black
2009-11-14	ARM: Fix up the implmentation of the msr instruction.	Gabe Black
2009-11-14	ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits.	Gabe Black
2009-11-14	ARM: Add a bitfield to indicate if an immediate should be used.	Gabe Black
2009-11-14	ARM: Write some functions to write to the CPSR and SPSR for instructions.	Gabe Black
2009-11-14	ARM: Fix up the implmentation of the mrs instruction.	Gabe Black
2009-11-14	ARM: More accurately describe the effects of using the control operands.	Gabe Black
2009-11-14	ARM: Hook up the moded versions of the SPSR.	Gabe Black
2009-11-14	ARM: Move around decoder to properly decode CP15	Ali Saidi
2009-11-10	ARM: Fix some bugs in the ISA desc and fill out some instructions.	Gabe Black
2009-11-10	ARM: Implement fault classes.	Gabe Black
2009-11-10	ARM: Fix the integer register indexes.	Gabe Black
2009-11-08	ARM: Support forcing load/store multiple to use user registers.	Gabe Black
2009-11-08	ARM: Simplify the load/store multiple generation code.	Gabe Black
2009-11-08	ARM: Split the condition codes out of the CPSR.	Gabe Black
2009-11-08	ARM: Add in more bits for the mon mode.	Gabe Black
2009-11-08	ARM: Get rid of NumInternalProcRegs.	Gabe Black
2009-11-08	ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR.	Gabe Black