gem5 - gem5

Age	Commit message (Expand)	Author
2013-02-15	arm: fix some fp comparisons that worked by accident.	Ali Saidi
2013-02-15	ARM: Fix an issue with clang generating wrong code.	Ali Saidi
2013-01-22	x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switch	Nilay Vaish
2013-01-12	x86: Changes to decoder, corrects 9376	Nilay Vaish
2013-01-08	arm: add access syscall for ARM SE mode	Mitch Hayenga
2013-01-07	arm: Invalidate cached TLB configuration in drainResume	Andreas Sandberg
2013-01-07	arm: Fix draining of the pagetable walker when squashing	Andreas Sandberg
2013-01-07	arm: Remove the register mapping hack used when copying TCs	Andreas Sandberg
2013-01-07	arch: Move the ISA object to a separate section	Andreas Sandberg
2013-01-07	base: Encapsulate the underlying fields in AddrRange	Andreas Hansson
2013-01-07	arm: Make ID registers ISA parameters	Andreas Sandberg
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
2013-01-07	o3: Fix issue with LLSC ordering and speculation	Ali Saidi
2013-01-04	Decoder: Remove the thread context get/set from the decoder.	Gabe Black
2013-01-04	ARM: Keep a copy of the fpscr len and stride fields in the decoder.	Gabe Black
2012-12-12	arm: set uopSet_uop as conditional or unconditional control	Nathanael Premillieu
2012-12-12	arm: set movret_uop as conditional or unconditional control	Nathanael Premillieu
2012-11-02	sim: Move the draining interface into a separate base class	Andreas Sandberg
2012-11-02	sim: Include object header files in SWIG interfaces	Andreas Sandberg
2012-11-02	ARM: dump stats and process info on context switches	Dam Sunwoo
2012-11-02	ISA: generic Linux thread info support	Dam Sunwoo
2012-10-25	arm: Use table walker clock that is inherited from CPU	Andreas Hansson
2012-10-15	Port: Add protocol-agnostic ports in the port hierarchy	Andreas Hansson
2012-10-15	Fix: Address a few minor issues identified by cppcheck	Andreas Hansson
2012-09-25	ARM: added support for flattened device tree blobs	Dam Sunwoo
2012-09-25	ARM: Squash outstanding walks when instructions are squashed.	Ali Saidi
2012-09-25	arm: Use a static_assert to test that miscRegName[] is complete	Andreas Sandberg
2012-09-25	ARM: Inst writing to cntrlReg registers not set as control inst	Nathanael Premillieu
2012-09-25	ARM: Predict target of more instructions that modify PC.	Ali Saidi
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2012-08-28	Clock: Rework clocks to avoid tick-to-cycle transformations	Andreas Hansson
2012-08-22	Packet: Remove NACKs from packet and its use in endpoints	Andreas Hansson
2012-08-15	O3,ARM: fix some problems with drain/switchout functionality and add Drain DP...	Anthony Gutierrez
2012-08-06	syscall emulation: Enabled getrlimit and getrusage for x86.	Marc Orr
2012-08-06	syscall emulation: Clean up ioctl handling, and implement for x86.	Marc Orr
2012-07-27	ARM: fix value of MISCREG_CTR returned by readMiscReg()	Anthony Gutierrez
2012-06-29	ARM: Fix identification of one RAS pop instruction.	Ali Saidi
2012-06-29	ARM: Update version of linux we claim to be to 3.0.0.	Ali Saidi
2012-06-29	ARM: Fix issue with predicted next pc being wrong because of advance() ordering.	Ali Saidi
2012-06-11	ARM: implement the ProcessInfo methods	Anthony Gutierrez
2012-06-05	cpu: Don't init simple and inorder CPUs if they are defered.	Anthony Gutierrez
2012-06-05	ISA: Back-out NoopMachInst as a StaticInstPtr change.	Ali Saidi
2012-06-05	ARM: removed extra white space	Chander Sudanthi
2012-06-05	ARM: Fix MPIDR and MIDR register implementation.	Chander Sudanthi
2012-06-05	O3: Clean up the O3 structures and try to pack them a bit better.	Ali Saidi
2012-06-05	ARM: Fix compilation on ARM after Gabe's change.	Ali Saidi
2012-05-26	ISA,CPU: Generalize and split out the components of the decode cache.	Gabe Black
2012-05-26	CPU: Merge the predecoder and decoder.	Gabe Black
2012-05-25	ISA: Make the decode function part of the ISA's decoder.	Gabe Black
2012-05-25	Decode: Make the Decoder class defined per ISA.	Gabe Black