| Age | Commit message (Expand) | Author |
|---|
| 2018-02-07 | arch-arm: Change function name for banked miscregs | Giacomo Travaglini |
| 2018-02-07 | arch-arm: Fix AArch32 SETEND Instruction | Giacomo Travaglini |
| 2018-02-07 | arch-arm: Correct Illegal Exception Return detection | Giacomo Travaglini |
| 2018-02-07 | arch-arm: ELUsingAArch32K from armarm pseudocode | Giacomo Travaglini |
| 2018-02-07 | arch-arm: isSecureBelow from armarm pseudocode | Giacomo Travaglini |
| 2018-02-07 | arch-arm: Fix incorrect assumptions in ELIs64 | Chuan Zhu |
| 2018-02-05 | arch-arm: Removing Serializing flag from ISB | Giacomo Travaglini |
| 2018-01-29 | arch-arm: understandably initialize register permissions | Curtis Dunham |
| 2018-01-29 | arm: extend MiscReg metadata structures | Curtis Dunham |
| 2018-01-29 | arch-arm: understandably initialize register mappings | Curtis Dunham |
| 2018-01-29 | arm: DT autogeneration - Generate memory node | Glenn Bergmans |
| 2018-01-29 | arm: DT autogeneration - Device Tree generation methods | Glenn Bergmans |
| 2018-01-20 | arch, mem: Make the page table lookup function return a pointer. | Gabe Black |
| 2018-01-20 | arm, base: Generalize and move the BitUnion hash struct. | Gabe Black |
| 2018-01-20 | base: Rework bitunions so they can be more flexible. | Gabe Black |
| 2018-01-20 | sim, arch, base: Refactor the base remote GDB class. | Gabe Black |
| 2018-01-19 | arch, mem, sim: Consolidate and rename the SE mode page table classes. | Gabe Black |
| 2018-01-15 | arch: Fix a fatal_if in most of the arch's process classes. | Gabe Black |
| 2018-01-11 | arm, power: Make the python TLB simobjects inherit from BaseTLB. | Gabe Black |
| 2018-01-11 | arch,mem: Remove the default value for page size. | Gabe Black |
| 2018-01-11 | arch,mem: Move page table construction into the arch classes. | Gabe Black |
| 2018-01-10 | style: change C/C++ source permissions to noexec | BKP |
| 2018-01-10 | alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT. | Gabe Black |
| 2018-01-09 | arm: Make translateFunctional override the base implementation. | Gabe Black |
| 2017-12-23 | alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst. | Gabe Black |
| 2017-12-22 | arch,cpu: "virtualize" the TLB interface. | Gabe Black |
| 2017-12-21 | arch-arm: Fixed WFE/WFI trapping behaviour | Giacomo Travaglini |
| 2017-12-21 | arch-arm: Hyp routed undef fault need to change its syndrome | Giacomo Travaglini |
| 2017-12-21 | arch-arm: Fix StaticInst encoding() method | Giacomo Travaglini |
| 2017-12-19 | arch-arm: Instruction size methods in StaticInst class | Giacomo Travaglini |
| 2017-12-19 | arch-arm: Change casting type from reinterpret to static | Giacomo Travaglini |
| 2017-12-14 | misc: Updates for gcc7.2 for x86 | Jason Lowe-Power |
| 2017-12-13 | arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with. | Gabe Black |
| 2017-12-08 | arm: Change access permission in TPIDRURO and TPIDRURW | Giacomo Travaglini |
| 2017-12-05 | arm: Add support for the dc {civac, cvac, cvau, ivac} instr | Nikos Nikoleris |
| 2017-12-05 | arm: Add support for the mcr dc{ic,i,c}mvac, dccmvau instructions | Nikos Nikoleris |
| 2017-12-05 | arm: Add CMO support for Non-Cacheable memory | Nikos Nikoleris |
| 2017-12-04 | misc: Rename misc.(hh|cc) to logging.(hh|cc) | Gabe Black |
| 2017-12-01 | arm: Enable ns registers access in secure mode | Giacomo Travaglini |
| 2017-11-28 | arch-arm: Add haveEL pseudocode function | Giacomo Travaglini |
| 2017-11-28 | arch-arm: Add assertions when extracting an ArmSystem from a TC | Giacomo Travaglini |
| 2017-11-22 | arch-arm: Add support for the brk instruction | Andreas Sandberg |
| 2017-11-22 | arch-arm: HVC instruction undefined in secure EL1 | Giacomo Travaglini |
| 2017-11-21 | arch-arm: ArmPMU refactor | Jose Marinho |
| 2017-11-21 | arch-arm: Do not increment PMU cycle event in WFI/WFE | Jose Marinho |
| 2017-11-21 | arch-arm: Fix MCR/MRC disassemble | Giacomo Travaglini |
| 2017-11-21 | arch-arm: Fix MSR/MRS disassemble | Giacomo Travaglini |
| 2017-11-20 | arch-arm: Ensure counters keep events on checkpoint resume | Jose Marinho |
| 2017-11-17 | sim: Implement load_addr_mask auto-calculation | Geoffrey Blake |
| 2017-11-16 | arch, arm: Print value being ignored on DummyISA write | Sean McGoogan |
