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path: root/src/arch/arm
AgeCommit message (Expand)Author
2011-10-09SE/FS: Build the Interrupt objects in SE mode.Gabe Black
2011-09-27Faults: Replace calls to genMachineCheckFault with M5PanicFault.Gabe Black
2011-09-26ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.Gabe Black
2011-09-19PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts.Gabe Black
2011-09-18Pseudoinst: Add an initParam pseudo inst function.Gabe Black
2011-09-13ARM: update TLB to set request packet ASID fieldDaniel Johnson
2011-09-13CP15 c15: enable execution with accesses to c15 registersChander Sudanthi
2011-09-13ARM: Implement numcpus bits in L2CTLR register.Daniel Johnson
2011-09-13LSQ: Only trigger a memory violation with a load/load if the value changes.Ali Saidi
2011-09-09StaticInst: Merge StaticInst and StaticInstBase.Gabe Black
2011-09-09Decode: Pull instruction decoding out of the StaticInst class into its own.Gabe Black
2011-08-19ARM: Mark some variables uncacheable until boot all CPUs are enabled.Ali Saidi
2011-08-19ARM: Add VExpress_E support with PCIe to gem5Ali Saidi
2011-08-19ARM: Add support for Versatile Express boardsAli Saidi
2011-08-19ARM: Add support for DIV/SDIV instructions.Ali Saidi
2011-08-19Fix bugs due to interaction between SEV instructions and O3 pipelineGeoffrey Blake
2011-08-19ARM: Fix a memory leak with the table walker.Ali Saidi
2011-07-15ARM: Fix SWP/SWPB undefined instruction behaviorWade Walker
2011-07-15ARM: Add two unimplemented miscellaneous registers.Wade Walker
2011-07-05ISA parser: Define operand types with a ctype directly.Gabe Black
2011-07-02ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.Gabe Black
2011-07-02ISA: Use readBytes/writeBytes for all instruction level memory operations.Gabe Black
2011-06-19cpus/isa: add a != operator for pcstateKorey Sewell
2011-06-17ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.Gedare Bloom
2011-06-16ARM: Handle case where new TLB size is different from previous TLB size.Ali Saidi
2011-06-16ARM: Fix memset on TLB flush and initializationChander Sudanthi
2011-06-02scons: rename TraceFlags to DebugFlagsNathan Binkert
2011-06-02copyright: clean up copyright blocksNathan Binkert
2011-05-23O3: Fix issue with interrupts/faults occuring in the middle of a macro-opGeoffrey Blake
2011-05-18gcc: fix an uninitialized variable warning from G++ 4.5Nathan Binkert
2011-05-13ARM: Generate condition code setting code based on which codes are set.Ali Saidi
2011-05-13ARM: Construct the predicate test register for more instruction programatically.Ali Saidi
2011-05-13ARM: Further break up condition code into NZ, C, V bits.Ali Saidi
2011-05-13ARM: Remove the saturating (Q) condition code from the renamed register.Ali Saidi
2011-05-13ARM: Break up condition codes into normal flags, saturation, and simd.Ali Saidi
2011-05-13Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.Chander Sudanthi
2011-05-13ARM: Better RealView/Versatile EB platform support.Chander Sudanthi
2011-05-04ARM: Add support for loading the a bootloader and configuring parameters for itAli Saidi
2011-05-04ARM: Implement WFE/WFI/SEV semantics.Prakash Ramrakhyani
2011-05-04ARM: Add support for MP misc regs and broadcast flushes.Ali Saidi
2011-05-04ARM: Add vfpv3 support to native trace.Ali Saidi
2011-05-04ARM: Fix small bug with vcvt instructionAli Saidi
2011-04-20fix some build problems from prior changesetsNathan Binkert
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-04-15includes: sort all includesNathan Binkert
2011-04-10ARM: Fix checkpoint restoration in ARM_SE.Ali Saidi
2011-04-10ARM: Get rid of some comments/todos that no longer apply.Ali Saidi
2011-04-04ARM: Use CPU local lock before sending load to mem system.Ali Saidi
2011-04-04ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.Ali Saidi
2011-04-04ARM: Fix bug in MicroLdrNeon templates for initiateAcc().Ali Saidi