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AgeCommit message (Expand)Author
2018-09-19syscall_emul: expand AuxVector classBrandon Potter
2018-09-13Fix SConstruct for asan buildEarl Ou
2018-09-13arch-arm: Correction for address size in EL1&0 translationAnouk Van Laer
2018-09-13arch-arm: Correction to address size in EL2/EL3Anouk Van Laer
2018-09-12dev-arm: rename Pl390 to GicV2Ciro Santilli
2018-09-10dev-arm: Factory SimObject for generating ArmInterruptPinGiacomo Travaglini
2018-09-10arm: Use the interrupt adaptor in the PMUAndreas Sandberg
2018-09-10arm: Add support for tracking TCs in ISA devicesAndreas Sandberg
2018-08-10arm: Add support for RCpc load-acquire instructions (ARMv8.3)Giacomo Gabrielli
2018-08-02arch-arm: Don't fail to initialise PMU if BP is missingAndreas Sandberg
2018-07-16arch-arm: Introduce ARMv8.1 Virtual Timer System RegistersGiacomo Travaglini
2018-07-16arch-arm: Introduce RAS System RegistersGiacomo Travaglini
2018-06-28arch-arm: Fix incorrect t{0,1}sz field in TTBCRAndreas Sandberg
2018-06-22arch-arm: AArch32 execution triggering AArch64 SW BreakGiacomo Travaglini
2018-06-22arch-arm: BadMode checking if corresponding EL is implementedGiacomo Travaglini
2018-06-14arch-arm: Adapting IllegalExecution fault for AArch32Giacomo Travaglini
2018-06-14arch-arm: Add Illegal Execution flag to PCStateGiacomo Travaglini
2018-06-14arch-arm: Read APSR in User ModeGiacomo Travaglini
2018-06-13arch-arm: Fix missing Request allocationGiacomo Travaglini
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
2018-06-11misc: Substitute pointer to Request with aliased RequestPtrGiacomo Travaglini
2018-06-06arch-arm: Remove dead doingStage2 variable in PT walkerAndreas Sandberg
2018-06-06arch-arm: Perform stage 2 lookups using the EL2 stateAndreas Sandberg
2018-06-06arch-arm: Respect EL from translation typeAndreas Sandberg
2018-06-06arch-arm: Fix page size handling when merging stage 1 and 2Andreas Sandberg
2018-06-06dev, arm: Add support for HYP & secure timersAndreas Sandberg
2018-06-06arch-arm: Adjust breakpoint EC depending on source stateAndreas Sandberg
2018-05-29arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOPGiacomo Travaglini
2018-05-29arch-arm: Remove unusued MISCREG_A64_UNIMPLGiacomo Travaglini
2018-05-29arch-arm: MPIDR.MT = 1 in a multithreaded systemGiacomo Travaglini
2018-05-29arch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation definedGiacomo Travaglini
2018-05-29arch-arm: Implement ARMv8.1 TTBR1_EL2 registerGiacomo Travaglini
2018-05-29arch-arm: Add E2H bit to HCR_EL2 System registerGiacomo Travaglini
2018-05-16arch-arm: Fix semihosting arg count for SYS_GET_CMDLINEAndreas Sandberg
2018-05-16arch-arm: Add support for semihosting STDIO redirectionAndreas Sandberg
2018-05-08arch-arm: Map ID_x_EL1 registers to AArch32 versionGiacomo Travaglini
2018-04-27sim,cpu,mem,arch: Introduced MasterInfo data structureGiacomo Travaglini
2018-04-19arch-arm: Add ARMv8.1 TTBR1_EL2 registerGiacomo Travaglini
2018-04-19arch-arm: Fix Unknown Instruction disassembleGiacomo Travaglini
2018-04-19arch-arm: Change disassemble when MSR to UNKNOWN registerGiacomo Travaglini
2018-04-18arch-arm: Fix masking in CPACR_EL1Chuan Zhu
2018-04-18arch-arm: Mask out unsupported trapped exception handling bitsChuan Zhu
2018-04-18arch-arm: Fix FPEXC32_EL2 to FPEXC mappingChuan Zhu
2018-04-18arch-arm: Adding MiscReg Priv (EL1) global flagGiacomo Travaglini
2018-04-18arch-arm: Correct masking of cp10 and cp11 in CPACRChuan Zhu
2018-04-18arch-arm: Using explicit invalidation in TLBGiacomo Travaglini
2018-04-17arch-arm: Fix secure MiscReg access when EL3 is not AArch32Giacomo Travaglini
2018-04-10arch-arm: Fix mrc,mcr to cop14 disassembleGiacomo Travaglini
2018-04-06arch-arm: Add support for Tarmac trace generationGiacomo Travaglini
2018-04-06arch-arm: Add support for Tarmac trace-based simulationGiacomo Travaglini
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