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AgeCommit message (Expand)Author
2018-05-29arch-arm: MPIDR.MT = 1 in a multithreaded systemGiacomo Travaglini
2018-05-29arch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation definedGiacomo Travaglini
2018-05-29arch-arm: Implement ARMv8.1 TTBR1_EL2 registerGiacomo Travaglini
2018-05-29arch-arm: Add E2H bit to HCR_EL2 System registerGiacomo Travaglini
2018-05-16arch-arm: Fix semihosting arg count for SYS_GET_CMDLINEAndreas Sandberg
2018-05-16arch-arm: Add support for semihosting STDIO redirectionAndreas Sandberg
2018-05-08arch-arm: Map ID_x_EL1 registers to AArch32 versionGiacomo Travaglini
2018-04-27sim,cpu,mem,arch: Introduced MasterInfo data structureGiacomo Travaglini
2018-04-19arch-arm: Add ARMv8.1 TTBR1_EL2 registerGiacomo Travaglini
2018-04-19arch-arm: Fix Unknown Instruction disassembleGiacomo Travaglini
2018-04-19arch-arm: Change disassemble when MSR to UNKNOWN registerGiacomo Travaglini
2018-04-18arch-arm: Fix masking in CPACR_EL1Chuan Zhu
2018-04-18arch-arm: Mask out unsupported trapped exception handling bitsChuan Zhu
2018-04-18arch-arm: Fix FPEXC32_EL2 to FPEXC mappingChuan Zhu
2018-04-18arch-arm: Adding MiscReg Priv (EL1) global flagGiacomo Travaglini
2018-04-18arch-arm: Correct masking of cp10 and cp11 in CPACRChuan Zhu
2018-04-18arch-arm: Using explicit invalidation in TLBGiacomo Travaglini
2018-04-17arch-arm: Fix secure MiscReg access when EL3 is not AArch32Giacomo Travaglini
2018-04-10arch-arm: Fix mrc,mcr to cop14 disassembleGiacomo Travaglini
2018-04-06arch-arm: Add support for Tarmac trace generationGiacomo Travaglini
2018-04-06arch-arm: Add support for Tarmac trace-based simulationGiacomo Travaglini
2018-04-06arch-arm: Fix AArch32 branch instructions disassembleGiacomo Travaglini
2018-04-06arch-arm: Fix secure write of SCTLR when EL3 is AArch64Giacomo Travaglini
2018-04-06arch-arm: Correct mcrr,mrrc disassembleGiacomo Travaglini
2018-03-26arch: Fix all override related warnings.Gabe Black
2018-03-26arch: Add a virtual asBytes function to the StaticInst class.Gabe Black
2018-03-23arch-arm: Distinguish IS TLBI from non-ISGiacomo Travaglini
2018-03-23arch-arm: Created function for TLB ASID InvalidationGiacomo Travaglini
2018-03-20arch, arm: Fix implicit-fallthrough GCC warningsChun-Chen Hsu
2018-03-15arm: Fix implicit-fallthrough warnings when building with gcc-7+Siddhesh Poyarekar
2018-03-15arch-arm: Fix unused variable warning in faults.ccNikos Nikoleris
2018-03-14arm: Fix maybe-uninitialized GCC warningsChun-Chen Hsu
2018-03-14arch-arm: ERET from AArch64 to AArch32 ignore MSBsGiacomo Travaglini
2018-03-12arch-arm: Adding IPA-Based Invalidating instructionsGiacomo Travaglini
2018-03-12arch-arm: Implement missing aarch32 TLBI registersGiacomo Travaglini
2018-03-08arch-arm: Enable Debug IFSC when faulting to aarch64 modeGiacomo Travaglini
2018-03-08arch-arm: Fix FSC generation in AbortFaultGiacomo Travaglini
2018-03-08arch-arm: Introduce update method in ArmFault classGiacomo Travaglini
2018-03-08arch-arm: Fix PCAlignmentFault routing to HypervisorGiacomo Travaglini
2018-03-06arm: Remove ignored const qualifierSiddhesh Poyarekar
2018-02-20arch-arm: Make hlt64 a mem barrier with semihostingGiacomo Travaglini
2018-02-20arch-arm: Add AArch32 HLT Semihosting interfaceGiacomo Travaglini
2018-02-20arch-arm: Add AArch32 SVC Semihosting interfaceGiacomo Travaglini
2018-02-20arch-arm: Adding isa templates for semihosting opsGiacomo Travaglini
2018-02-20arch-arm: HLT using immediate when checking for semihostingGiacomo Travaglini
2018-02-20arch-arm: Fix Hlt64,Svc64,Hvc64,Smc64,Brk64 disassemblyGiacomo Travaglini
2018-02-19arch-arm: Semihosting not available in syscall emulationGiacomo Travaglini
2018-02-19arch-arm: Add support for secure state in semihostingAndreas Sandberg
2018-02-19arch-arm: Add aarch64 semihosting supportAndreas Sandberg
2018-02-16arch-arm: IMPLEMENTATION DEFINED registerGiacomo Travaglini
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