| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2010-06-02 | ARM: Replace the "never" condition with the "unconditional" condition. | Gabe Black | |
| 2010-06-02 | ARM: Add a base class for 32 bit thumb data processing immediate instructions. | Gabe Black | |
| 2010-06-02 | ARM: Add a function to decode 32 bit thumb immediate values. | Gabe Black | |
| 2010-06-02 | ARM: Expand the decoding for 32 bit thumb data processing immediate ↵ | Gabe Black | |
| instructions. | |||
| 2010-06-02 | ARM: Stub out the 32 bit Thumb portion of the decoder. | Gabe Black | |
| 2010-06-02 | ARM: Add bitfields for 32 bit thumb. | Gabe Black | |
| 2010-06-02 | ARM: Decode VFP instructions. | Gabe Black | |
| 2010-06-02 | ARM: Stub out the 16 bit thumb decoder. | Gabe Black | |
| 2010-06-02 | ARM: Add thumb bitfields to the ExtMachInst and the isa definition. | Gabe Black | |
| 2010-06-02 | ARM: Make the decoder handle thumb instructions separately. | Gabe Black | |
| --HG-- rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/armdecode.isa rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/thumbdecode.isa | |||
| 2010-06-02 | ARM: Add a thumb bit bitfield. | Gabe Black | |
| 2010-06-02 | ARM: Make the predecoder handle Thumb instructions. | Gabe Black | |
| 2010-06-02 | ARM: Make sure ExtMachInst is used consistently instead of regular MachInst. | Gabe Black | |
| 2010-06-02 | ARM: Add a bitfield for setting the regular, inst bits of an ExtMachInst. | Gabe Black | |
| 2010-06-02 | ARM: Add a bit to the ExtMachInst to select thumb mode. | Gabe Black | |
| 2010-06-02 | ARM: Allow ARM processes to start in Thumb mode. | Gabe Black | |
| 2010-06-02 | ARM: Add a new base class for instructions that can do an interworking branch. | Gabe Black | |
| 2010-06-02 | ARM: Track the current ISA mode using the PC. | Gabe Black | |
| 2010-06-02 | ARM: Remove IsControl from operands that don't imply control transfers. | Gabe Black | |
| Also remove IsInteger from CondCodes. | |||
| 2010-03-23 | cpu: fix exec tracing memory corruption bug | Steve Reinhardt | |
| Accessing traceData (to call setAddress() and/or setData()) after initiating a timing translation was causing crashes, since a failed translation could delete the traceData object before returning. It turns out that there was never a need to access traceData after initiating the translation, as the traced data was always available earlier; this ordering was merely historical. Furthermore, traceData->setAddress() and traceData->setData() were being called both from the CPU model and the ISA definition, often redundantly. This patch standardizes all setAddress and setData calls for memory instructions to be in the CPU models and not in the ISA definition. It also moves those calls above the translation calls to eliminate the crashes. | |||
| 2010-02-12 | O3PCU: Split loads and stores that cross cache line boundaries. | Timothy M. Jones | |
| When each load or store is sent to the LSQ, we check whether it will cross a cache line boundary and, if so, split it in two. This creates two TLB translations and two memory requests. Care has to be taken if the first packet of a split load is sent but the second blocks the cache. Similarly, for a store, if the first packet cannot be sent, we must store the second one somewhere to retry later. This modifies the LSQSenderState class to record both packets in a split load or store. Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA to indicate whether unaligned memory accesses are allowed. This is used throughout the changed code so that compiler can optimise away code dealing with split requests for ISAs that don't need them. | |||
| 2009-11-17 | ARM: Begin implementing CP15 | Ali Saidi | |
| 2009-11-17 | ARM: Differentiate between LDM exception return and LDM user regs. | Ali Saidi | |
| 2009-11-17 | ARM: Boilerplate full-system code. | Ali Saidi | |
| --HG-- rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc rename : src/arch/sparc/system.cc => src/arch/arm/system.cc rename : src/arch/sparc/system.hh => src/arch/arm/system.hh rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh | |||
| 2009-11-16 | imported patch isa_fixes2.diff | Ali Saidi | |
| 2009-11-15 | ARM: Make the exception return form of ldm restore CPSR. | Gabe Black | |
| 2009-11-15 | ARM: Create a new type of load uop that restores spsr into cpsr. | Gabe Black | |
| 2009-11-14 | ARM: Check in the actual change from the last commit. | Gabe Black | |
| The last commit was somehow empty. This was what was supposed to go in it. | |||
| 2009-11-14 | ARM: Fix up the implmentation of the msr instruction. | Gabe Black | |
| 2009-11-14 | ARM: Define a mask to differentiate purely CPSR bits from CondCodes bits. | Gabe Black | |
| 2009-11-14 | ARM: Add a bitfield to indicate if an immediate should be used. | Gabe Black | |
| 2009-11-14 | ARM: Write some functions to write to the CPSR and SPSR for instructions. | Gabe Black | |
| 2009-11-14 | ARM: Fix up the implmentation of the mrs instruction. | Gabe Black | |
| 2009-11-14 | ARM: More accurately describe the effects of using the control operands. | Gabe Black | |
| 2009-11-14 | ARM: Hook up the moded versions of the SPSR. | Gabe Black | |
| These registers can be accessed directly, or through MISCREG_SPSR which will act as whichever SPSR is appropriate for the current mode. | |||
| 2009-11-14 | ARM: Move around decoder to properly decode CP15 | Ali Saidi | |
| 2009-11-10 | ARM: Fix some bugs in the ISA desc and fill out some instructions. | Gabe Black | |
| 2009-11-10 | ARM: Implement fault classes. | Gabe Black | |
| Implement some fault classes using the curriously recurring template pattern, similar to SPARCs. | |||
| 2009-11-10 | ARM: Fix the integer register indexes. | Gabe Black | |
| The PC indexes in the various register sets was defined in the section for unaliased registers which was throwing off the indexing. This moves those where they belong. Also, to make detecting accesses to the PC easier and because it's in the same place in all modes, the intRegForceUser function now passes it through as index 15. | |||
| 2009-11-08 | ARM: Support forcing load/store multiple to use user registers. | Gabe Black | |
| 2009-11-08 | ARM: Simplify the load/store multiple generation code. | Gabe Black | |
| Specifically, get rid of the big switch statement so more cases can be handled. Enumerating all the possible settings doesn't scale well. Also do some minor style clean up. | |||
| 2009-11-08 | ARM: Split the condition codes out of the CPSR. | Gabe Black | |
| This allows those bits to be renamed while allowing the other fields to control the behavior of the processor. | |||
| 2009-11-08 | ARM: Add in more bits for the mon mode. | Gabe Black | |
| 2009-11-08 | ARM: Get rid of NumInternalProcRegs. | Gabe Black | |
| That constant is a carry over from Alpha and doesn't do anything in ARM. | |||
| 2009-11-08 | ARM: Add back in spots for Rhi and Rlo, and use a named constant for LR. | Gabe Black | |
| 2009-11-08 | ARM: Get rid of the Raddr operand. | Gabe Black | |
| 2009-11-08 | ARM: Initialize processes in user mode. | Gabe Black | |
| I accidentally left in a change to test using int registers in system mode. This change reverts that. | |||
| 2009-11-08 | ARM: Implement the shadow registers using register flattening. | Gabe Black | |
| 2009-11-08 | ARM: Set up an intregs.hh for ARM. | Gabe Black | |
| Add constants for all the modes and registers, maps for aliasing, functions that use the maps and range check, and use a named constant instead of a magic number for the microcode register. | |||
| 2009-11-07 | ARM: Get rid of some unneeded register indexes. | Gabe Black | |
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index : gem5 | |
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