index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
arch
/
arm
Age
Commit message (
Expand
)
Author
2018-10-19
arm: update hint instruction decoding to match ARMv8.5
Ciro Santilli
2018-10-17
arch: Get rid of the unused type AnyReg.
Gabe Black
2018-10-12
syscall_emul: update arm uname release to 3.7.0+
Ciro Santilli
2018-10-09
arch-arm: Add have_crypto System parameter
Giacomo Travaglini
2018-10-09
arch-arm: AArch64 Crypto AES
Giacomo Travaglini
2018-10-09
arch-arm: AArch64 Crypto SHA
Giacomo Travaglini
2018-10-09
arch-arm: AArch32 Crypto AES
Matt Horsnell
2018-10-09
arch-arm: AArch32 Crypto SHA
Matt Horsnell
2018-10-08
dev, arm: remove the RealViewEB platform
Ciro Santilli
2018-10-08
arch-arm: Mark ArmProcess method as override
Matteo Andreozzi
2018-10-02
sim-se: Set ArmProcess64 hwcaps depending on ID regs
Giacomo Travaglini
2018-10-02
sim-se: Different HWCAP for ArmProcess32/64
Giacomo Travaglini
2018-10-02
arch-arm: Add FP16 support introduced by Armv8.2-A
Edmund Grimley Evans
2018-10-02
arch-arm: Add FP16 support and other primitives to fplib
Edmund Grimley Evans
2018-10-01
arch-arm: Implement AArch64 ID regs as bitunions
Giacomo Travaglini
2018-10-01
arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register
Giacomo Travaglini
2018-10-01
arch-arm: Move MiscReg BitUnions into a separate header file
Giacomo Travaglini
2018-10-01
arch-arm: Init AArch64 ID registers in SE mode
Giacomo Travaglini
2018-09-28
arch-arm: raise/clear IRQ when writing to PMOVSCLR/SET
Giacomo Travaglini
2018-09-19
syscall_emul: expand AuxVector class
Brandon Potter
2018-09-13
Fix SConstruct for asan build
Earl Ou
2018-09-13
arch-arm: Correction for address size in EL1&0 translation
Anouk Van Laer
2018-09-13
arch-arm: Correction to address size in EL2/EL3
Anouk Van Laer
2018-09-12
dev-arm: rename Pl390 to GicV2
Ciro Santilli
2018-09-10
dev-arm: Factory SimObject for generating ArmInterruptPin
Giacomo Travaglini
2018-09-10
arm: Use the interrupt adaptor in the PMU
Andreas Sandberg
2018-09-10
arm: Add support for tracking TCs in ISA devices
Andreas Sandberg
2018-08-10
arm: Add support for RCpc load-acquire instructions (ARMv8.3)
Giacomo Gabrielli
2018-08-02
arch-arm: Don't fail to initialise PMU if BP is missing
Andreas Sandberg
2018-07-16
arch-arm: Introduce ARMv8.1 Virtual Timer System Registers
Giacomo Travaglini
2018-07-16
arch-arm: Introduce RAS System Registers
Giacomo Travaglini
2018-06-28
arch-arm: Fix incorrect t{0,1}sz field in TTBCR
Andreas Sandberg
2018-06-22
arch-arm: AArch32 execution triggering AArch64 SW Break
Giacomo Travaglini
2018-06-22
arch-arm: BadMode checking if corresponding EL is implemented
Giacomo Travaglini
2018-06-14
arch-arm: Adapting IllegalExecution fault for AArch32
Giacomo Travaglini
2018-06-14
arch-arm: Add Illegal Execution flag to PCState
Giacomo Travaglini
2018-06-14
arch-arm: Read APSR in User Mode
Giacomo Travaglini
2018-06-13
arch-arm: Fix missing Request allocation
Giacomo Travaglini
2018-06-11
misc: Using smart pointers for memory Requests
Giacomo Travaglini
2018-06-11
misc: Substitute pointer to Request with aliased RequestPtr
Giacomo Travaglini
2018-06-06
arch-arm: Remove dead doingStage2 variable in PT walker
Andreas Sandberg
2018-06-06
arch-arm: Perform stage 2 lookups using the EL2 state
Andreas Sandberg
2018-06-06
arch-arm: Respect EL from translation type
Andreas Sandberg
2018-06-06
arch-arm: Fix page size handling when merging stage 1 and 2
Andreas Sandberg
2018-06-06
dev, arm: Add support for HYP & secure timers
Andreas Sandberg
2018-06-06
arch-arm: Adjust breakpoint EC depending on source state
Andreas Sandberg
2018-05-29
arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOP
Giacomo Travaglini
2018-05-29
arch-arm: Remove unusued MISCREG_A64_UNIMPL
Giacomo Travaglini
2018-05-29
arch-arm: MPIDR.MT = 1 in a multithreaded system
Giacomo Travaglini
2018-05-29
arch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation defined
Giacomo Travaglini
[next]