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2018-10-08arch-arm: Mark ArmProcess method as overrideMatteo Andreozzi
Allows compilation on clang3.5+ by fixing Winconsistent-missing-override Change-Id: Ic0ebf3869fc2d9a29fcf7cf5a6535952f41714d0 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13227 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-02sim-se: Set ArmProcess64 hwcaps depending on ID regsGiacomo Travaglini
ArmProcess64 needs to query AArch64 ID registers to check which hw capability is going to report in the appropriate aux vector's entry. Change-Id: I1e1294b831e902226f9b162f25e841e53b940454 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13164 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-10-02sim-se: Different HWCAP for ArmProcess32/64Giacomo Travaglini
AArch32 and AArch64 have different HWCAP flags in Linux, but we are currently using AArch32 HWCAP flags to initialize the aux vector of both AArch32 and AArch64 binaries. This patch also fixes a bug that was introduced by running in SE mode a target binary compiled with glibc > 2.18. Using AArch32 flags resulted on CPUID flag being set for AArch64. This incorrectly tells libc that emulation of the midr_el1 is supported. In FullSystem this might work, but since we are in Syscall Emulation there is no OS behind emulating the mrs midr_el1 instruction. By separating AArch32 flags from AArch64 flags we are turning off the CPUID hwcap flag in SE mode. Change-Id: I9f651957ba9d19dc2bc06606de070c6586f0f9fa Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/12884 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com>
2018-10-02arch-arm: Add FP16 support introduced by Armv8.2-AEdmund Grimley Evans
This changeset adds support for FP/SIMD instructions with half-precision floating-point operands. Change-Id: I4957f111c9c5e5d6a3747fe9d169d394d642fee8 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13084 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-02arch-arm: Add FP16 support and other primitives to fplibEdmund Grimley Evans
This changeset: - extends fplib to support emulation of half-precision floating-point (FP16) operations; - extends fplib to support additional primitives introduced by the Arm Scalable Vector Extension (SVE) (fplibExpa, fplibScale, fplibTrigMAdd, fplibTrigSMul, fplibTrigSSel); - adds the FZ16 bit to FPSCR; - cleans up fplib code by replacing constants with preprocessor macros and by adding inline functions to recognise NaNs and infinities. Change-Id: If8fdb2a5824b478c8310bbc126ec60cc1105f135 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13044 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01arch-arm: Implement AArch64 ID regs as bitunionsGiacomo Travaglini
This patch is implementing the following AArch64 ID registers as bitunions, so that it is easier to query for feature availability: - ID_AA64DFR0_EL1 - ID_AA64ISAR0_EL1 - ID_AA64ISAR1_EL1 - ID_AA64MMFR1_EL1 - ID_AA64MMFR2_EL1 - ID_AA64PFR0_EL1 They are updated to the latest Armv8.5 arch release version. RES0 only ID registers like ID_AA64AFR1_EL1 haven't been added. Change-Id: Ied037abe3757421bcfc2834d397a8cf9a2b9f0a7 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13067 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 registerGiacomo Travaglini
This patch implements AArch64 Memory Model Feature Register 2 (from ARMv8.2) Change-Id: I16d9acaf620fac6d1206e208bd143daec1657daf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13066 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01arch-arm: Move MiscReg BitUnions into a separate header fileGiacomo Travaglini
As the number of MiscRegs increases there is the need of a cleaner header file; this patch is separating miscreg.[cc,hh] where the miscreg decoding/utility functions are defined/declared from the MiscReg register types (BitUnion). Change-Id: I815f53b117b50e47f93aa13d78356ef09d2a2541 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13065 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-10-01arch-arm: Init AArch64 ID registers in SE modeGiacomo Travaglini
One of the auxv vector's flag is the HWCAP, whose bits match the content of several arm ID registers. This patch factors out AArch64 ID registers init into a separate method and creates the symmetric AArch32 ID register init as well, so that we get a meaningful auxiliary vector in SE mode. Change-Id: I52bdb31b67508c4447558ebd7ca743733a69280e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13064 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-28arch-arm: raise/clear IRQ when writing to PMOVSCLR/SETGiacomo Travaglini
Writing a 1 to the Overflow Flag Status register should trigger an interrupt raise/clear depending on the register we are currently using (PMOVSCLR for clearing and PMOVSSET for raising). Change-Id: I2091456685a245712045cf7a4932ac36b7dded1d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12531 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-19syscall_emul: expand AuxVector classBrandon Potter
The AuxVector class is responsible for holding Process data. The data that it holds is normally setup by an OS kernel in the process address space. The purpose behind doing this is to pass in information that the process will need for various reasons. (Check out the enum in the header file for an idea of what the AuxVector holds.) The AuxVector struct was changed into a class and encapsulation methods were added to protect access to the member variables. The host ISA may have a different endianness than the simulated ISA. Since data is passed between the process address space and the simulator for auxiliary vectors, we need to worry about maintaining endianness for the right context. Change-Id: I32c5ac4b679559886e1efeb4b5483b92dfc94af9 Reviewed-on: https://gem5-review.googlesource.com/12109 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-09-13Fix SConstruct for asan buildEarl Ou
Sometimes it's easier to debug gem5 built with ASan enabled. This CL fixes some build error when using --with-asan. Bug: None Test: ./scripts/build_gem5 --with-asan --with-ubsan build/ARM/gem5.debug Change-Id: Iaaaaebc3f25749e11f97bf454ddd0153b3de56e7 Reviewed-on: https://gem5-review.googlesource.com/12511 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-09-13arch-arm: Correction for address size in EL1&0 translationAnouk Van Laer
When doing EL0/1 translation in stage2, the physical address size will be defined by the hypervisor (via VTCR_EL2.ps, not TCR.ips). See D10.2.121 of the ARM ARM. Change-Id: Ic7df97c0f5950a648f7408cde3955a640b562c1d Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12552 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-09-13arch-arm: Correction to address size in EL2/EL3Anouk Van Laer
This commit corrects how the address size is determined in EL2/EL3. Previously, TCR_ELx.ips was used but this should be TCR_ELx.ps. Change-Id: I7e5a2f376335532a1d1c8c74d12a416617474ae2 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12551 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-09-12dev-arm: rename Pl390 to GicV2Ciro Santilli
The Pl390 model has evolved and acquired a lot of the features from GICv2, which means that the name is no longer appropriate. Rename it to GICv2 since this is more representative of the supported features. GICv2 is backwards compatible with the older Pl390, so we decided to simply rename the class to represent both GICv2 and older interfaces such as the instead of creating a new separate one. Change-Id: I1c05fba8b3cb5841c66480e9f05b8c873eba3229 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12492 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-10dev-arm: Factory SimObject for generating ArmInterruptPinGiacomo Travaglini
With this patch the python ArmInterruptPin SimObject matches to the C++ ArmInterruptPinGen. The latter is in charge of generating the ArmInterruptPin (which is not a SimObject anymore). This is meant to ease the generation of ArmInterruptPins: by not being SimObjects we are not forced to instantiate them in the configuration script; we can generate them dynamically instead throughout simulation. Change-Id: I917d73a26168447221f5993c8ae975ee3771e3bf Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12401 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-10arm: Use the interrupt adaptor in the PMUAndreas Sandberg
Rewrite interrupt handling in the PMU model to use the new interrupt adaptor. Change-Id: I2cbb99580c46d3e21a1335b897843b7b6e41f10c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12400 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-09-10arm: Add support for tracking TCs in ISA devicesAndreas Sandberg
ISA devices typically need to keep track of the thread context they are associated with. Among other things, this is required for interrupt delivery. Add a BaseISADevice:setThreadContext() method to wire such models to the right thread context. Change-Id: Iad354d176c0c4c4e34c6ab8b5acaee0b69da0406 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/12399 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-08-10arm: Add support for RCpc load-acquire instructions (ARMv8.3)Giacomo Gabrielli
Please note that at the moment these instructions behave like the existing load-acquire instructions, which follow the more conservative RCsc consistency model. This means that the new instructions are _functionally_ correct, but the potential performance improvements enabled by the RCpc model will not be experienced in timing simulations. Change-Id: I04c786ad2941072bf28feba7d2ec6e142c8b74cb Reviewed-by: Andreas Hansson <andreas.hansson@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11989 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-08-02arch-arm: Don't fail to initialise PMU if BP is missingAndreas Sandberg
The branch predictor currently assumes that each CPU has a branch predictor. This isn't true in some cases (e.g., KVM, Atomic). Change-Id: I61e80dca940c2dadba1b812449691c9dba1c06d9 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11520 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-07-16arch-arm: Introduce ARMv8.1 Virtual Timer System RegistersGiacomo Travaglini
Adding CNTHV_CTL_EL2, CNTHV_CVAL_EL2, CNTHV_TVAL_EL2 System Registers into the decode tree. They are currently implemented as a generic timer and produces a warning if accessed. Change-Id: I1a23035d67f95eeac49d890283e9a0d58426d504 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11592 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-07-16arch-arm: Introduce RAS System RegistersGiacomo Travaglini
Adding RAS Extension System Registers into the decode tree. They are currently unimplemented and produce a warning (not failure) if accessed. Change-Id: I4baeded822c9582a2cb9d5277409b029eb00a962 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11591 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-28arch-arm: Fix incorrect t{0,1}sz field in TTBCRAndreas Sandberg
The t0sz and t1sz fields in TTBCR only are only three bits wide unlike aarch64 which has a 6-bit wide field. The higher bits of the aarch64-equivalent should be treated as RES0. Change-Id: I60df73105c34500c0348a44a491c117e9b28f18f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11589 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-22arch-arm: AArch32 execution triggering AArch64 SW BreakGiacomo Travaglini
AArch32 Software Breakpoint (BKPT) can trigger an AArch64 fault when interprocessing if the trapping conditions are met. Change-Id: I485852ed19429f9cd928a6447a95eb6f471f189c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11197 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-22arch-arm: BadMode checking if corresponding EL is implementedGiacomo Travaglini
The old utility function called badMode was only checking if the mode passed as an argument was a recognized mode. It was not checking if the corresponding mode/EL was implemented. That function has been renamed to unknownMode and a new badMode has been introduced. This is used by the cpsrWriteByInstruction function. In this way any try to change the execution mode won't succeed if the mode hasn't been implemented. Change-Id: Ibfe385c5465b904acc0d2eb9647710891d72c9df Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11196 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-14arch-arm: Adapting IllegalExecution fault for AArch32Giacomo Travaglini
The Illegal Execution fault triggered by the setting of processor state PSTATE.IL happens in AArch32 as well and takes the form of UNDEFINED exception fault. We are hence copying the UndefinedInstruction AArch32 fields into the IllegalInstSetStateFault. Change-Id: Ibb7424397c2030ea5d010577c530277a27036aea Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10814 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-14arch-arm: Add Illegal Execution flag to PCStateGiacomo Travaglini
This patch moves the detection of the Illegal Execution flag (PSTATE.IL) from the tlb translation stage (fetch) to the decoding stage. This is done by adding the illegalExecution field to the PCState. Change-Id: I9c1c4e9c6bd5ded905c1d56b3034e4e9322582fa Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10813 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-14arch-arm: Read APSR in User ModeGiacomo Travaglini
This patch substitutes reads to the CPSR in user mode (MRS CPSR) to reads to APSR (Application Program Status Register). This is the user level alias for the CPSR. The APSR is a subset of the CPSR. Change-Id: I18a70693aef6fd305a4c4cb3c6f81f331bc60a2d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10602 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-13arch-arm: Fix missing Request allocationGiacomo Travaglini
This patch is fixing a missing allocation for a Request buffer in the Stage2Translation class. Change-Id: I9ce7b85d3527c5b3cc895eb83e9a39641793b0bd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11095 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
This patch is changing the underlying type for RequestPtr from Request* to shared_ptr<Request>. Having memory requests being managed by smart pointers will simplify the code; it will also prevent memory leakage and dangling pointers. Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10996 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-06-11misc: Substitute pointer to Request with aliased RequestPtrGiacomo Travaglini
Every usage of Request* in the code has been replaced with the RequestPtr alias. This is a preparing patch for when RequestPtr will be the typdefed to a smart pointer to Request rather then a raw pointer to Request. Change-Id: I73cbaf2d96ea9313a590cdc731a25662950cd51a Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10995 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-06-06arch-arm: Remove dead doingStage2 variable in PT walkerAndreas Sandberg
Change-Id: Iab5ecec56120c725847b2e462fd4793cfac87d3c Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10815
2018-06-06arch-arm: Perform stage 2 lookups using the EL2 stateAndreas Sandberg
Change-Id: Ic56b694f22a26e9c208a10e5703d4b5b0900070f Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10507 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-06arch-arm: Respect EL from translation typeAndreas Sandberg
There are cases where instructions request translations in the context of a lower EL. This is currently not respected in the TLB and the page table walker. Fix that. Change-Id: Icd59657a1ecfd8bd75a001bb1a4e41a6f4808a36 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10506 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-06arch-arm: Fix page size handling when merging stage 1 and 2Andreas Sandberg
The current code to merge translation entries from stage 1 and stage 2 doesn't handle cases where the page sizes at the different stages differ. This change fixes both the case when the hypervisor has a larger page size and when it has a smaller page size. Change-Id: Icdf289005bf1e4de4d91d54643924a38d9d77796 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10505 Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-06dev, arm: Add support for HYP & secure timersAndreas Sandberg
Change-Id: I1a4849283f9bd5b1856e1378f7cefc33fc14eebd Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Curtis Dunham <curtis.dunham@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10023 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-06-06arch-arm: Adjust breakpoint EC depending on source stateAndreas Sandberg
The software breakpoint exception class needs to be adjusted depending on the source EL's execution state. This change fixes an incorrect exception class when taking a breakpoint from aarch64. Change-Id: I99d87a04be6bf9ce3a69f6b19969fa006cfd63a4 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10809 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-05-29arch-arm: ISA param for treating MISCREG_IMPDEF_UNIMPL as NOPGiacomo Travaglini
In the Arm ISA there are some sys reg numbers which are reserved for implementation defined registers. The default behaviour is to to treat them as unimplemented registers. It is now possible to change this behaviour at runtime and treat them as NOP. In this way an access to those register won't make simulation fail. Change-Id: I0d108299a6d5aa81fcdabdaef04eafe46df92343 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10504 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-29arch-arm: Remove unusued MISCREG_A64_UNIMPLGiacomo Travaglini
In case the decoder fails to find a suitable MiscReg during a MSR/MRS in AArch64, MISCREG_UNKNOWN is used, so there is no need for an extra MISCREG_A64_UNIMPL register. Change-Id: I7c709fc554e554b39d765dffb7ceb90e33b7c15f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10503 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-29arch-arm: MPIDR.MT = 1 in a multithreaded systemGiacomo Travaglini
MPIDR.MT Indicates whether the lowest level of affinity consists of logical PEs that are implemented using a multithreading type approach Change-Id: Ia5e6e65577729c7826227c4574ce690f76454edc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10502 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-29arch-arm: S3_<op1>_<Cn>_<Cm>_<op2> are Implementation definedGiacomo Travaglini
In the AArch64 ISA, S3_<op1>_<Cn>_<Cm>_<op2> refers to a pool of implementation defined registers, provided that reg numbers are in the following range: <op1> is in the range 0 - 7 <CRn> can take the values 11, 15 <CRm> is in the range 0 - 15 <op2> is in the range 0 - 7 Change-Id: I7edd013e5cea4887f5e4c5a81f4835b7de93bd50 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10501 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-29arch-arm: Implement ARMv8.1 TTBR1_EL2 registerGiacomo Travaglini
This patch implements the ARMv8.1 TTBR1_EL2 register, which is used for getting the translation table base address when a Host Operating System is running at EL2. (HCR_EL2.E2H = 1) Change-Id: Ic0ab351cae3fd64855eda7c18c8757da0d7b8663 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10382 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-29arch-arm: Add E2H bit to HCR_EL2 System registerGiacomo Travaglini
This patch adds the EL2 Host bit to the HCR_EL2 register. Enables a configuration where a Host Operating System is running in EL2, and the Host Operating System's applications are running in EL0. Change-Id: I92d21ed9f8958c58f135dca1b6a97460ba4c02f9 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10381 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-05-16arch-arm: Fix semihosting arg count for SYS_GET_CMDLINEAndreas Sandberg
SYS_GET_CMDLINE was declared as having 1 parameter when it is really supposed to have two parameters. Change-Id: Ia364abb4b34834f4d5e598b5adee9585e0815ac8 Reported-by: Steve Capper <steve.capper@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10022 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-05-16arch-arm: Add support for semihosting STDIO redirectionAndreas Sandberg
The Arm Semihosting layer currently assumes that the guest application shares STDIO with gem5. This makes it hard to distinguish application output from gem5's output and makes it impossible to redirect STDIN when running in interactive mode. Add support for custom STDIO redirection when instantiating the Semihosting model. Change-Id: I3411a6b9bfb008ffc3087d8837f59be72bd1e8ae Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com> Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10021 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2018-05-08arch-arm: Map ID_x_EL1 registers to AArch32 versionGiacomo Travaglini
AArch64 ID_x_EL1 registers map to AArch32 ID_x counterparts. Those registers must be initialized even when the highest Exception Level is using AArch64. Change-Id: Iccc9b6f631f5fac288116eb1ef2ad1d30c03de7b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10361 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-27sim,cpu,mem,arch: Introduced MasterInfo data structureGiacomo Travaglini
With this patch a gem5 System will store more info about its Masters. While it was previously keeping track of the Master name and Master ID only, it is now adding a per-Master pointer to the SimObject related to the Master. This will make it possible for a client to query a System for a Master using either the master's name or the master's pointer. Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/9781 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-04-19arch-arm: Add ARMv8.1 TTBR1_EL2 registerGiacomo Travaglini
This patch adds ARMv8.1 TTBR1_EL2 register into the decodeAArch64SysReg table, but stil leaving it unimplemented (Accessing it through MSR/MRS causes an exception) Change-Id: I463b86cc544233aa1ee5b2fcba689d6b9f2a874b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10063 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-19arch-arm: Fix Unknown Instruction disassembleGiacomo Travaglini
Do not print the entire ExtMachInst when disassembling an Unknown Instruction. Change-Id: Icd5908ec0fa430090165b2426372bdeb43c2a155 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10062 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-04-19arch-arm: Change disassemble when MSR to UNKNOWN registerGiacomo Travaglini
This patch changes the fault being thrown when MSR/MRS to an unknown Misc register in AArch64. While previously the instruction was decoded as an Unknown instruction (hence not printing any information), it is now decoded as a FailUnimplemented and the unrecognized System register numbers (CRn, op0...) are printed. Change-Id: I205ff7adcde5934231c77e8d2250db69a34581fc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10061 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 02:56:40 +0000