| Age | Commit message (Expand) | Author |
|---|
| 2020-01-07 | arch,sim: Stop decoding the pseudo inst subfunc value. | Gabe Black |
| 2020-01-06 | arch,sim: Use the guest ABI mechanism with pseudo instructions. | Gabe Black |
| 2020-01-06 | arch-arm: Semihosting, specify files root dir | Adrian Herrera |
| 2019-12-30 | fastmodel: Fix compilation errors | Chun-Chen TK Hsu |
| 2019-12-27 | fastmodel: Move ARM but not CortexA76 specific bits to the IRIS TC. | Gabe Black |
| 2019-12-27 | fastmodel: Move the ARM IRIS threadcontext into CortexA76. | Gabe Black |
| 2019-12-27 | fastmodel: Mostly collapse ARM base classes for the CortexA76 CPU. | Gabe Black |
| 2019-12-27 | fastmodel: Checkpoint the TCs when checkpointing a fast model CPU. | Gabe Black |
| 2019-12-27 | fastmodel: Handle "special" vector regs without calling into IRIS. | Gabe Black |
| 2019-12-24 | fastmodel: Implement readVecRegFlat for ArmThreadContext. | Gabe Black |
| 2019-12-24 | fastmodel: Determine what space to use for breakpoints dynamically. | Gabe Black |
| 2019-12-23 | fastmodel: Implement PC based events. | Gabe Black |
| 2019-12-20 | arch-arm: Fix clang warnings | Jui-min Lee |
| 2019-12-19 | arch-arm: Fix decoding of LDFF1x scalar plus scalar | Adrià Armejach |
| 2019-12-18 | arch-arm: Semihosting, fix SYS_FLEN | Adrian Herrera |
| 2019-12-18 | arch-arm: Secure EL2 checking | Adrian Herrera |
| 2019-12-18 | arch-arm: AArch64 trap check, arbitrary ECs/Imms | Adrian Herrera |
| 2019-12-17 | fastmodel: Tell fast model not to shutdown when time stops. | Gabe Black |
| 2019-12-17 | fastmodel: Implement port proxies. | Gabe Black |
| 2019-12-17 | fastmodel: Create a TLB model which uses IRIS to do translations. | Gabe Black |
| 2019-12-17 | fastmodel: Add an address translation mechanism to the ThreadContext. | Gabe Black |
| 2019-12-17 | fastmodel: Add a header for IRIS MSN constants. | Gabe Black |
| 2019-12-11 | arch-arm: Always initialize SVE memData | Giacomo Travaglini |
| 2019-12-11 | arch-arm: Avoid creating an empty byteEnable vector | Giacomo Travaglini |
| 2019-12-10 | sim,arch: Collapse the ISA specific versions of m5Syscall. | Gabe Black |
| 2019-12-10 | arch,cpu,sim: Push syscall number determination up to processes. | Gabe Black |
| 2019-12-10 | arch: Get rid of the now unused setSyscallArg. | Gabe Black |
| 2019-12-10 | arch: Use ignoreWarnOnceFunc instead of the WarnOnce flag. | Gabe Black |
| 2019-12-10 | arch-arm: Disambuiguate NumFloatV7ArchRegs usage | Giacomo Travaglini |
| 2019-12-10 | arch-arm: Unify VLdmStm behaviour when reg out of index | Giacomo Travaglini |
| 2019-12-10 | arch-arm: Fix NumVecV7ArchRegs value (64->16) | Giacomo Travaglini |
| 2019-12-10 | arch-arm: Reorder arch/arm/registers.hh constants | Giacomo Travaglini |
| 2019-12-10 | arch-arm: Replace NumFloatV8ArchRegs with NumVecV8ArchRegs | Giacomo Travaglini |
| 2019-12-06 | kvm,arm: Update the KVM ARM v8 CPU to use vector regs. | Gabe Black |
| 2019-12-03 | fastmodel: Switch the diagnostic pragmas to GCC from clang. | Gabe Black |
| 2019-12-03 | systemc,fastmodel: Use the gem5_scons error and warning functions. | Gabe Black |
| 2019-12-03 | fastmodel: Suppress a spurious warning on clang for amba_pv.h. | Gabe Black |
| 2019-11-28 | arm: Make sure not to shift off of the end of a uint32_t in KVM. | Gabe Black |
| 2019-11-26 | arch-arm: Make the Tarmac parsed registers case insensitive | Giacomo Travaglini |
| 2019-11-26 | arch,cpu: Get rid of ISA_HAS_CC_REGS and its associated ifdefs. | Gabe Black |
| 2019-11-25 | arm: Stop serializing ISA values wihch are cached from the system. | Gabe Black |
| 2019-11-25 | arch-arm: default MIDR for Armv8 ISA processors | Adrian Herrera |
| 2019-11-18 | arch: Get rid of the (Big|Little)EndianGuest namespaces. | Gabe Black |
| 2019-11-18 | arch: Make and use endian specific versions of the mem helpers. | Gabe Black |
| 2019-11-18 | arch-arm: R/W interface to AArch32 HCR2 misc reg | Adrian Herrera |
| 2019-11-18 | arch-arm: Fix short descriptors cacheability during table walks | Giacomo Travaglini |
| 2019-11-18 | arch-arm: Fix long descriptors cacheability during table walks | Giacomo Travaglini |
| 2019-11-14 | arch-arm: Refactor code to check if gic is GicV2 | Chun-Chen TK Hsu |
| 2019-11-14 | config: Add fastmodel cluster in fs_bigLITTLE.py | Chun-Chen TK Hsu |
| 2019-11-13 | arm: Replace most htog and gtoh with htole and letoh. | Gabe Black |
