| Age | Commit message (Expand) | Author |
|---|
| 2019-11-05 | arch-arm: Annotate original address in CMOs | Giacomo Travaglini |
| 2019-11-02 | arch,cpu: Move endianness conversion of inst bytes into the ISA. | Gabe Black |
| 2019-11-01 | arch-arm: generic method for getting an ArmSystem | Adrian Herrera |
| 2019-10-31 | fastmodel: Add CortexA76x[234] models. | Gabe Black |
| 2019-10-31 | fastmodel: Enable auto bridging and use it to simplify CortexA76x1. | Gabe Black |
| 2019-10-31 | fastmodel: Templatize the xn versions of the CortexA76. | Gabe Black |
| 2019-10-30 | arch,sim: Make copyStringArray take an explicit endianness. | Gabe Black |
| 2019-10-30 | arch: Make endianness a property of the OS class syscalls can consume. | Gabe Black |
| 2019-10-30 | fastmodel: Refactor the CortexA76x1 model for MP support. | Gabe Black |
| 2019-10-30 | fastmodel: Helper function to setup FastModels for simulation | Chun-Chen TK Hsu |
| 2019-10-25 | cpu: Get rid of the nextInstEventCount method. | Gabe Black |
| 2019-10-25 | cpu: Get rid of the serviceInstCountEvents method. | Gabe Black |
| 2019-10-25 | fastmodel: Use getCurrentInstCount for totalInsts(). | Gabe Black |
| 2019-10-25 | fastmodel: Implement getCurrentInstCount. | Gabe Black |
| 2019-10-25 | cpu: Switch off of the CPU's comInstEventQueue. | Gabe Black |
| 2019-10-25 | cpu: Make the ThreadContext a PCEventScope. | Gabe Black |
| 2019-10-25 | cpu: Create a PCEventScope class to abstract the scope of PCEvents. | Gabe Black |
| 2019-10-23 | fastmodel: Add string constructors which delegate to const char * ones. | Gabe Black |
| 2019-10-23 | arch: Drop sysctl support if built against glibc | Tommaso Marinelli |
| 2019-10-19 | cpu,arm: Push the stage 2 MMUs out of the CPU into the TLBs. | Gabe Black |
| 2019-10-19 | arch: Make a base class for Interrupts. | Gabe Black |
| 2019-10-17 | arm: Don't force the ArmISA::TLB in vtophys.cc. | Gabe Black |
| 2019-10-16 | arch,base,sim: Move Process loader hooks into the Process class. | Gabe Black |
| 2019-10-15 | arch,base: Restructure the object file loaders. | Gabe Black |
| 2019-10-14 | fastmodel: Expose all CPU communication ports from the GIC. | Gabe Black |
| 2019-10-12 | arch,base: Separate the idea of a memory image and object file. | Gabe Black |
| 2019-10-10 | arch,base: Stop loading the interpreter in ElfObject. | Gabe Black |
| 2019-10-10 | arch-arm: Move generateDtb to ArmSystem | Giacomo Travaglini |
| 2019-10-10 | dev-arm, configs: Remove RealViewPBX platform | Giacomo Travaglini |
| 2019-10-10 | arch, base: Stop assuming object files have three segments. | Gabe Black |
| 2019-10-09 | fastmodel: Export GICV3Comms directly. | Gabe Black |
| 2019-10-09 | base: Rename Section to Segment, and some of its members. | Gabe Black |
| 2019-10-07 | fastmodel: Make CortexA76x1's interrupts use gem5's mechanisms. | Gabe Black |
| 2019-10-07 | kvm, arm: fix the size of MISCREG_FPSR and MISCREG_FPCR | Ciro Santilli |
| 2019-10-03 | arch-arm: Annotate CM flag in AA64 CM Instructions | Giacomo Travaglini |
| 2019-10-03 | arch-arm: Set CM bit in DataAbort | Giacomo Travaglini |
| 2019-10-02 | arch-arm: Create helper for sending events (SEV) | Giacomo Travaglini |
| 2019-10-02 | fastmodel: Get rid of the back channel mem port in FastModel::ArmCPU. | Gabe Black |
| 2019-10-02 | fastmodel: Implement a custom sendFunctional for CortexA76x1. | Gabe Black |
| 2019-10-02 | fastmodel: Let the EVS set an attribute for getSendFunctional to return. | Gabe Black |
| 2019-10-01 | fastmodel: Add a gem5Cpu attribute to the CortexA76x1. | Gabe Black |
| 2019-10-01 | fastmodel: Add a utility class which makes it easier to watch signals. | Gabe Black |
| 2019-10-01 | fastmodel: Pull out and simplify the interrupt mechanism in the GIC. | Gabe Black |
| 2019-09-27 | fastmodel: Add glue code which adapts fastmodels to run in gem5. | Gabe Black |
| 2019-09-19 | arch-arm: PSTATE.PAN changes should inval cached regs in TLB | Giacomo Travaglini |
| 2019-09-18 | arch-arm: Fix Data Abort ISS when caused by Atomic operation | Giacomo Travaglini |
| 2019-09-18 | arch-arm: ISV bit in DataAbort should check for translation stage | Giacomo Travaglini |
| 2019-09-18 | arch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2.E2H=1 | Giacomo Travaglini |
| 2019-09-06 | arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 banking | Giacomo Travaglini |
| 2019-09-06 | arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64 banking | Giacomo Travaglini |
