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AgeCommit message (Expand)Author
2019-10-07fastmodel: Make CortexA76x1's interrupts use gem5's mechanisms.Gabe Black
2019-10-07kvm, arm: fix the size of MISCREG_FPSR and MISCREG_FPCRCiro Santilli
2019-10-03arch-arm: Annotate CM flag in AA64 CM InstructionsGiacomo Travaglini
2019-10-03arch-arm: Set CM bit in DataAbortGiacomo Travaglini
2019-10-02arch-arm: Create helper for sending events (SEV)Giacomo Travaglini
2019-10-02fastmodel: Get rid of the back channel mem port in FastModel::ArmCPU.Gabe Black
2019-10-02fastmodel: Implement a custom sendFunctional for CortexA76x1.Gabe Black
2019-10-02fastmodel: Let the EVS set an attribute for getSendFunctional to return.Gabe Black
2019-10-01fastmodel: Add a gem5Cpu attribute to the CortexA76x1.Gabe Black
2019-10-01fastmodel: Add a utility class which makes it easier to watch signals.Gabe Black
2019-10-01fastmodel: Pull out and simplify the interrupt mechanism in the GIC.Gabe Black
2019-09-27fastmodel: Add glue code which adapts fastmodels to run in gem5.Gabe Black
2019-09-19arch-arm: PSTATE.PAN changes should inval cached regs in TLBGiacomo Travaglini
2019-09-18arch-arm: Fix Data Abort ISS when caused by Atomic operationGiacomo Travaglini
2019-09-18arch-arm: ISV bit in DataAbort should check for translation stageGiacomo Travaglini
2019-09-18arch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2.E2H=1Giacomo Travaglini
2019-09-06arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 bankingGiacomo Travaglini
2019-09-06arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64 bankingGiacomo Travaglini
2019-09-06arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 bankingGiacomo Travaglini
2019-09-06arch-arm: MISCREG_ICC_BPR1_EL1 using AA64 bankingGiacomo Travaglini
2019-09-06arch-arm: Add explicit AArch64 MiscReg bankingGiacomo Travaglini
2019-09-06arch-arm: Use same template across all MSR instGiacomo Travaglini
2019-09-06arch-arm: SySDC64 Instructions (CMO) using MiscRegIndexGiacomo Travaglini
2019-09-06arch-arm: fix GDB stub after SVECiro Santilli
2019-09-06arch-arm: SGI registers undecoded in AArch32Giacomo Travaglini
2019-09-06arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC regsGiacomo Travaglini
2019-08-30arm,kvm: Fix python imports from global namespaceGiacomo Travaglini
2019-08-21arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0Ciro Santilli
2019-08-21arch-arm: Fix implicit fallthrough build errorsChun-Chen TK Hsu
2019-08-20arch-arm: Replace occ of opModeToEL(currOpMode/cpsr) with currELGiacomo Travaglini
2019-08-20arch-arm: Replace direct use cpsr.el with currEL helperGiacomo Travaglini
2019-08-20arch-arm: Overload currEL helper with CPSR argumentGiacomo Travaglini
2019-08-20arch-arm: Rewrite the currEL helper method to use opModeToELGiacomo Travaglini
2019-08-12arch-arm: Added LD/ST<op> atomic instruction family and SWP instrsJordi Vaquero
2019-08-12arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic funcJordi Vaquero
2019-08-07arch-arm: Add TypeAtomicOp class to be used by new atomic instructionsJordi Vaquero
2019-08-07arch-arm: adding register control flags enabling LSE implementationJordi Vaquero
2019-08-05arch-arm: Implement ARMv8.1-PAN, Privileged access neverGiacomo Travaglini
2019-08-05arch-arm: Rewrite MSR immediate instruction classGiacomo Travaglini
2019-07-27arch-arm: Fix reg dependency for SVE gather microopsGabor Dozsa
2019-07-27arch-arm: Fix tracing code for SVE gatherGabor Dozsa
2019-07-27arch-arm: Add SVE LD1RQ[BHWD]Javier Setoain
2019-07-27arch-arm: Fix decoding for SVE memory instructionsAdrià Armejach
2019-07-27arch-arm: Add support for SVE load/store structuresJavier Setoain
2019-07-19arch-arm: Implement ARMv8.1-HPD, Hierarchical permission disableGiacomo Travaglini
2019-07-19arch-arm: Add HPD bit for TCR_EL2/EL3Giacomo Travaglini
2019-07-19arch-arm: Clean Fault generation when processing Long DescriptorGiacomo Travaglini
2019-07-18arch-arm: Add first-/non-faulting load instructionsGabor Dozsa
2019-07-17arch-arm: Use ExceptionLevel type in TlbEntryGiacomo Travaglini
2019-06-26arch, arm: Update miscRegs in getTEAnouk Van Laer
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