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2019-10-07fastmodel: Make CortexA76x1's interrupts use gem5's mechanisms.Gabe Black
This makes it easier to wire up CPUs to the interrupt controller, and makes things more modular. Change-Id: I8d3ab26e4bb588b8efb198ed145d0f58b7ee04cb Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21049 Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-07kvm, arm: fix the size of MISCREG_FPSR and MISCREG_FPCRCiro Santilli
Those registers are 32-bit instead of 64 in the KVM API. The Linux kernel 5.2 linux/Documentation/virtual/kvm/api.txt contains: 0x6020 0000 0010 00d4 FPSR 32 fp_regs.fpsr 0x6020 0000 0010 00d5 FPCR 32 fp_regs.fpcr The register itself is 64-bit in the ARM manual, but the top 32 are RES0. This fixes the following error when running ARM KVM early in the simulation: panic: KVM: Failed to set register (0x60300000001000d4) value (errno: 22) Change-Id: I8fe6e12df4809992173200a42e3ce5414748bdad Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21300 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-03arch-arm: Annotate CM flag in AA64 CM InstructionsGiacomo Travaglini
DC ZVA instruction is not classified as a cache maintenance instruction, and therefore its execution cannot cause this field to be set to 1. Change-Id: I0f30db1e6fc629dc52293edfb2bac4cf99ee49cc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21306 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-03arch-arm: Set CM bit in DataAbortGiacomo Travaglini
The CM bit in a DataAbort ISS indicates whether the Data Abort came from a cache maintenance or address translation instruction. Change-Id: I8888520446550581c8dd0507a8989935db7047be Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21305 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-02arch-arm: Create helper for sending events (SEV)Giacomo Travaglini
Events can be generated by devices, so we need an interface devices can use to notify events to PEs. Change-Id: I330575e7d116388d5f9260ef4400b0feaa861f3e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21301 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-02fastmodel: Get rid of the back channel mem port in FastModel::ArmCPU.Gabe Black
This was to support port proxies and getInstPort and getDataPort. With some recent upstream changes, getInstPort and getDataPort are only used for CPU switching which we can't support (TLM ports are bound permanently), and with the sendFunctional delegate for port proxies, we don't need to have a traditional gem5 port lying around. This gets rid of the "mem" port and all its plumbing. Change-Id: Ic68a40a26b24aa05b33da0510c9f4b7621cbf578 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21048 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-02fastmodel: Implement a custom sendFunctional for CortexA76x1.Gabe Black
Change-Id: I28094620106a8edd90e1144b4fb87ae5729ebf32 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21047 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-02fastmodel: Let the EVS set an attribute for getSendFunctional to return.Gabe Black
The iris CPU model doesn't necessarily know the best way to send functional packets (what port? what type is that port?), but only has a generic sc_module pointer to the EVS and so can't call specialized methods on it. There also isn't any common base class for EVSes to cast into in a generic way. This attribute mechanism lets the EVS set up its own sendFunctional implementation however it needs to using facilities that are built into generic sc_objects. Change-Id: I69bf364908c2a5360bd6ce7d3e49ce67c6f771b0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21046 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-10-01fastmodel: Add a gem5Cpu attribute to the CortexA76x1.Gabe Black
This attribute is to let the fast model EVS CPU find and talk to the gem5 CPU in case it needs a pointer to one of its ThreadContexts for instance. Also move the code that finds the clock period attribute/event to the constructor. gem5 guarantees that the EVS is constructed before its pointer is passed to the iris CPU wrapper, and so the EVS will have had a chance to install those controls if it's going to. Change-Id: I389ef0ba0f9d528140f40444baa5091a9ec338cd Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21045 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-01fastmodel: Add a utility class which makes it easier to watch signals.Gabe Black
These signals come from the exported virtual subsystem and could signal interrupts, etc. The new SignalReceiver class makes it easier to watch those signals and perform some behavior when they change without having to bring along a lot of systemc baggage. Change-Id: I09651de1dd0e7340a61779aaf080c695ce299fd4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21043 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-01fastmodel: Pull out and simplify the interrupt mechanism in the GIC.Gabe Black
This change pulls out the SPI and PPI command structures and replaces them with a custom protocol which can deliver a SPI or PPI without having to bundle their parameters into a structure. Change-Id: I8f15c8b3182bd6560bf5ef0345b0bc64173def85 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21042 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-27fastmodel: Add glue code which adapts fastmodels to run in gem5.Gabe Black
Fast Models are models written by ARM which emulate different components of a computer system. They can be combined into small subsystems and then exported as systemc modules. To enable this code, you'll need to set USE_ARM_FASTMODEL variable to true. This CL does not include the fast models themselves, or a license to use them or the associated tools. To build these fast models, you'll need to set some scons variables. These variables should be set as described in the fast model distribution. * PVLIB_HOME * MAXCORE_HOME * ARMLMD_LICENSE_FILE Some minor patches to source filesdistributed with the fast model code may be necessary since their use of systemc is not necessarily 100% standards compliant. Change-Id: Id53814b95d8aa320da4d4f2159be0736fc12eb73 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20799 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-19arch-arm: PSTATE.PAN changes should inval cached regs in TLBGiacomo Travaglini
Change-Id: Id94e355fec345d2e952539a7dce7fbd21ed220c6 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20983 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-18arch-arm: Fix Data Abort ISS when caused by Atomic operationGiacomo Travaglini
Data Aborts caused by an atomic instruction have a special rule for their syndrome: From a ISS point of view they count as read if a read to that address would generate a fault; they count as writes otherwise (ISS.WnR bit) This patch is implementing this in the TLB. For permission faults we need to explicitly check if a read would trigger a fault (e.g. checking for the AP bits) since permissions can allow read-only accesses. For other MMU exceptions (like translation faults) we are confident the nature of the access doesn't affect the genration of a fault. This means that if the access is atomic, we treat it as a read from an ISS.WnR point of view. Change-Id: Ia524aa6ae07f81513cdc26c516b5fd9b01a931c3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20981 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-18arch-arm: ISV bit in DataAbort should check for translation stageGiacomo Travaglini
According to the ESR spec, the ISV bit is set to 1 only for stage 2 aborts. Change-Id: Id524ef36e82184f741e968ddba04ca8ccdd4ad58 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20980 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-18arch-arm: PSTATE.PAN affecting EL2 only when HCR_EL2.E2H=1Giacomo Travaglini
Change-Id: I6df0cdcbadca17f30d3de3bed887f75c739b00f0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20979 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 bankingGiacomo Travaglini
Change-Id: Ic08ac1e7f3ebef408a83aa068ce15e9dfe2aa3cd Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20628 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm, dev-arm: MISCREG_ICC_AP1R0_EL1 using AA64 bankingGiacomo Travaglini
Change-Id: Ide93464f62288fbe8f409f718487a15512c01295 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20627 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 bankingGiacomo Travaglini
Change-Id: Ib1691f1cba08251a36ceb959849b61c33cc3e93b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20626 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: MISCREG_ICC_BPR1_EL1 using AA64 bankingGiacomo Travaglini
Change-Id: Ib30c7a49490f05f88ddfd7572dd360cb92647f81 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20625 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: Add explicit AArch64 MiscReg bankingGiacomo Travaglini
Change-Id: I89836d14491a51b1573f45c8012e3ad12b107d24 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20623 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: Use same template across all MSR instGiacomo Travaglini
Change-Id: Ifb9f1db288e401761b71ccf426e370c475e5663f Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20622 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: SySDC64 Instructions (CMO) using MiscRegIndexGiacomo Travaglini
Change-Id: Ia66d6abf965b1d33579e8fa048608d99c93ff2ce Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20621 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-09-06arch-arm: fix GDB stub after SVECiro Santilli
The SVE patches made registers longer by increasing NumVecElemPerVecReg, but the GDB XML was not updated to account for that, and as a result GDB connections were failing with: Remote 'g' packet reply is too long This commit introduces NumVecElemPerSimdVecReg which counts only the SIMD register sizes to get it back working. SVE GDB support is not added here. Change-Id: I4191b9f1999ae02b0308863db4cc9b5b16a27d6d Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20468 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: SGI registers undecoded in AArch32Giacomo Travaglini
Change-Id: I64d3e639e1beaa507263637d59499aafeb5a19f8 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20612 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-09-06arch-arm: Fix read/setMiscReg for AArch32 GICv3 ICC regsGiacomo Travaglini
The readMiscReg/setMiscReg methods were not forwarding register reads/writes to the cpu interface when in AArch32. Change-Id: Ide983e793b8033a88d31fe6ea87eaeffe9b093f5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20611 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-08-30arm,kvm: Fix python imports from global namespaceGiacomo Travaglini
Change-Id: I31bd3563c2427efd7e520f714b1ca6f480fa4e85 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20491 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-21arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0Ciro Santilli
In src/cpu/reg_class.hh, numPinnedWrites was unset because the constructors were not well factored out. Change-Id: Ib2fc8d34a1adf5c48826d257a31dd24dfa64a08a Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20048 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-21arch-arm: Fix implicit fallthrough build errorsChun-Chen TK Hsu
1942b21713 introduced implicit-fallthrough errors when compiled with GCC 8. This change adds M5_UNREACHABLE in the default case. Change-Id: I220f2b3fe39b5c3a65c0dd390915bffeafb28962 Signed-off-by: Chun-Chen TK Hsu <chunchenhsu@google.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20268 Reviewed-by: Jordi Vaquero <jordi.vaquero@metempsy.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20arch-arm: Replace occ of opModeToEL(currOpMode/cpsr) with currELGiacomo Travaglini
Change-Id: I739a9be03ea5caa63540c62fd110eee86a058c4c Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20252 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20arch-arm: Replace direct use cpsr.el with currEL helperGiacomo Travaglini
The patch is replacing it in places where the current EL could be using AArch32, hence leading to an incorrect ExceptionLevel. Change-Id: I99b75af2668f2c38fd88bec62e985ab7dbea80dc Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20251 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20arch-arm: Overload currEL helper with CPSR argumentGiacomo Travaglini
Change-Id: I1edabc61637ecb9d30bca34b5dbcf1de12b35fe0 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20250 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-20arch-arm: Rewrite the currEL helper method to use opModeToELGiacomo Travaglini
Direct use of cpsr.el should be discouraged: it should be used when in AArch64 only; when in AArch32 it won't return the matching EL. Eg: when in Supervisor Mode (EL1), CPSR.M<3,0> (mode) is 0b0011, and cpsr.el will return 0 (EL0) Change-Id: I5504bd1f59980f79b2607cce435ea09245de12e5 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20249 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-12arch-arm: Added LD/ST<op> atomic instruction family and SWP instrsJordi Vaquero
Adding LD/ST/SWP family of instructions, LD/ST include a set of operations like ADD/CLR/EOR/SET/UMAX/UMIN/SMAX/SMIN This commit includes: + Instruction decode + Instruction functional code + New set of skeletons for Ex/Com/Ini/Constructor and declaration. Change-Id: Ieea8d4256807e004d2f8aca8f421b3df8d76b116 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19812 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-08-12arch-arm: Adding CAS/CASP AMO instr including new TypedAtomic funcJordi Vaquero
CAS/CASP atomic instruction implementation This change includes: + Instructions decode + new amo64.isa file where CAS/CASP main functional code is implemented + mem64.isa include Execute/complete/initiatie skeletons, contructor and declarator + Added TypedAtomic function for pair register CASP instruction Change-Id: I4a4acdec4ab1c8b888f10ef5dc1e896be8c432bf Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19811 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-08-07arch-arm: Add TypeAtomicOp class to be used by new atomic instructionsJordi Vaquero
Creating a new object TypeAtomicOp that will be used by the atomic instructions following gem5 AMO feature. Change-Id: If082b596fb37d7a1cb569a4320c23505591df6a5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19810 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-07arch-arm: adding register control flags enabling LSE implementationJordi Vaquero
Added changes on arch-arm architecture to accept Atomic instructions following ARM v8.1 documentation. That includes enabling atomic bit in ID registers and add have_lse variable into arm system. Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19809 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-05arch-arm: Implement ARMv8.1-PAN, Privileged access neverGiacomo Travaglini
ARMv8.1-PAN adds a new bit to PSTATE. When the value of this PAN state bit is 1, any privileged data access from EL1 or EL2 to a virtual memory address that is accessible at EL0 generates a Permission fault. This feature is mandatory in ARMv8.1 implementations. This feature is supported in AArch64 and AArch32 states. The ID_AA64MMFR1_EL1.PAN, ID_MMFR3_EL1.PAN, and ID_MMFR3.PAN fields identify the support for ARMv8.1-PAN. Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Change-Id: I94a76311711739dd2394c72944d88ba9321fd159 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19729 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-08-05arch-arm: Rewrite MSR immediate instruction classGiacomo Travaglini
MSR <pstatefield>, #imm is used for setting a PSTATE field using an immediate. Current implementation has the following flaws: * There is no base MSR immediate definition: all the existing PSTATE fields have a different class definition * Those implementation make use of a generic data64 base class which results in a wrong disassembly (pstate register is printed as an integer register). This patch is fixing this by defining a new base class (MiscRegImmOp64) and new related templates. In this way, we aim to ease addition of new PSTATE fields (in ARMv8.x) Change-Id: I71b630ff32abe1b105bbb3ab5781c6589b67d419 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19728 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-27arch-arm: Fix reg dependency for SVE gather microopsGabor Dozsa
The first microop of an SVE gather creates a copy of the source vecreg into AA64FpUreg0. The subsequent microops must refer to this copy as a source in order to establish the correct register dependencies. Change-Id: I84d8c331f9f9ebca609948a15f686a7cde67dc31 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19172 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-27arch-arm: Fix tracing code for SVE gatherGabor Dozsa
Printing the entire contents of the dest vecreg for each gather microop is suboptimal as it creates false positive differences between Atomic and O3 traces. This fix prints only the memory data which a microop loads from memory. Change-Id: Idd8e0b26a96f9c9cc0b69360174bedf6a9f6dcb5 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19171 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-27arch-arm: Add SVE LD1RQ[BHWD]Javier Setoain
Add both scalar+scalar and scalar+immediate versions. Change-Id: If5fa1a71ab0dab93f9d35b544ea0899ece858bea Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19170 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-07-27arch-arm: Fix decoding for SVE memory instructionsAdrià Armejach
Some SVE memory instructions are missing the makeSP function for register operands that can be the SP register. This leads to segmentation faults on the application side as the wrong register is decoded. Change-Id: Ic71abc845e0786a60d665231b5f7b024d2955f4b Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19169 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-07-27arch-arm: Add support for SVE load/store structuresJavier Setoain
Change-Id: I4d9cde18dfc3d478eacc156de6a4a9721eb9e2ff Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13524 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-07-19arch-arm: Implement ARMv8.1-HPD, Hierarchical permission disableGiacomo Travaglini
According to the armarm: ARMv8.1-HPD introduces the facility to disable the hierarchical attributes, APTable, PXNTable, and UXNTable, in the translation tables. This disable has no effect on the NSTable bit. This feature is mandatory in ARMv8.1 implementations. This feature is added only to the VMSAv8-64 translation regimes. ARMv8.2 extends this to the AArch32 translation regimes, see ARMv8.2-AA32HPD. The ID_AA64MMFR1_EL1.HPDS field identifies the support for ARMv8.1-HPD. Change-Id: Ibbf589b82f2c1e4437b43252f8f633e8f6fb0b80 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19610 Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-19arch-arm: Add HPD bit for TCR_EL2/EL3Giacomo Travaglini
This is controlling Hierarchical Permissions for EL3 and for EL2 when HCR_EL2.E2H = 0. Change-Id: I9d6615ff4980cc56a28dc32088cf1524155f0fa4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19609 Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-19arch-arm: Clean Fault generation when processing Long DescriptorGiacomo Travaglini
A new shared method has been introduced: generateLongDescFault Change-Id: I7eb6fa1347a6c2cf9cb11fd9f2137d983c4f7a40 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19608 Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-18arch-arm: Add first-/non-faulting load instructionsGabor Dozsa
First-/non-faulting loads are part of Arm SVE. Change-Id: I93dfd6d1d74791653927e99098ddb651150a8ef7 Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19177 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-07-17arch-arm: Use ExceptionLevel type in TlbEntryGiacomo Travaglini
Replacing uint8_t with ExceptionLevel type in the arm TlbEntry. The variable is representing the translation regime it is targeting. Change-Id: Ifcd6e86c5d73f752e8476a2b7fda9ea74a0c7a3b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19488 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-06-26arch, arm: Update miscRegs in getTEAnouk Van Laer
Normally, a translation will start via translateTiming/functional which will check if the miscRegs have been updated and if so, will update the TLB state accordingly. However, in a 2 stage system, if there is a hit in stage 1, the resulting IPA will be sent to the S2-TLB for translation via a getTE() function call (via the stage2_lookup object). This will cause the state of the S2-TLB to be out of sync. Change-Id: I117e4032fc76d7d31f4f999887b5573a7e5811e6 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/14995 Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 10:34:30 +0000