| Age | Commit message (Expand) | Author |
|---|
| 2019-04-25 | arch-arm: Correct target EL field in TLBI operations | Giacomo Travaglini |
| 2019-04-11 | arch-arm: Enable PMSELR_EL0 read in PMU | Giacomo Travaglini |
| 2019-04-02 | dev-arm: Make GICv3 maintenance interrupt an ArmInterrupt | Giacomo Travaglini |
| 2019-04-01 | dev-arm: Correct cast of template parameter | Andrea Mondelli |
| 2019-03-28 | arch-arm: Fix use of bitwise operators on booleans | Javier Setoain |
| 2019-03-28 | arch-arm: Fix index generation for VecElem operands | Giacomo Travaglini |
| 2019-03-25 | arch-arm: Add missing fall-through defaults | Javier Setoain |
| 2019-03-22 | sim-se: Fixed initialization array size | Tiago Muck |
| 2019-03-21 | dev-arm: ambiguous use of getPort() | Andrea Mondelli |
| 2019-03-19 | arch, cpu, dev, gpu, mem, sim, python: start using getPort. | Gabe Black |
| 2019-03-14 | arch-arm,cpu: Add initial support for Arm SVE | Giacomo Gabrielli |
| 2019-03-11 | arch-arm: Fixing implicit fallthrough build errors | Ryan Gambord |
| 2019-03-01 | mem-cache: alias to mem::getMasterPort in TLB class | Andrea Mondelli |
| 2019-03-01 | arch-arm: implement floating point aarch32 VCVTA family | Ciro Santilli |
| 2019-02-18 | arch-arm: Move GICv3 detection at startup time | Giacomo Travaglini |
| 2019-02-13 | sim-se: update the arm kernel version | Ayaz Akram |
| 2019-02-12 | python: Don't assume SimObjects live in the global namespace | Andreas Sandberg |
| 2019-02-08 | arch-arm: Fix Virtual interrupts in AArch64 | Giacomo Travaglini |
| 2019-02-08 | arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30 | Giacomo Travaglini |
| 2019-02-08 | arch-arm: Allow ArmPPI usage for PMU | Giacomo Travaglini |
| 2019-02-08 | arch-arm: Fix initialization of PMU counters | Ruben Ayrapetyan |
| 2019-02-01 | cpu, arch: Replace the CCReg type with RegVal. | Gabe Black |
| 2019-01-31 | arch: cpu: Rename *FloatRegBits* to *FloatReg*. | Gabe Black |
| 2019-01-30 | arch,cpu: Add vector predicate registers | Giacomo Gabrielli |
| 2019-01-30 | arch-arm, configs: Create single instance of DTB autogeneration | Giacomo Travaglini |
| 2019-01-25 | arch-arm: Remove floatReg operand type | Giacomo Travaglini |
| 2019-01-25 | arch-arm: Use VecElem instead of FloatReg for FP instruction | Giacomo Travaglini |
| 2019-01-25 | cpu, arch, arch-arm: Wire unused VecElem code in the O3 model | Giacomo Travaglini |
| 2019-01-25 | arch-arm: Inital vector rename mode depending on A32/A64 | Giacomo Travaglini |
| 2019-01-25 | arch-arm: Remove unused float operands | Giacomo Travaglini |
| 2019-01-23 | arch-arm: Implement LoadAcquire/StoreRelease in AArch32 | Giacomo Travaglini |
| 2019-01-23 | arch-arm: IsStoreConditional flag set depending on flavor | Giacomo Travaglini |
| 2019-01-23 | arch-arm: Remove SWP and SWPB instructions | Giacomo Travaglini |
| 2019-01-23 | arm: Replace MiscReg with RegVal in utility.(hh|cc). | Gabe Black |
| 2019-01-22 | arch: cpu: Stop passing around misc registers by reference. | Gabe Black |
| 2019-01-22 | arm: Get rid of some register type definitions. | Gabe Black |
| 2019-01-22 | arch-arm: implement the GDB XML target description for ARM | Ciro Santilli |
| 2019-01-22 | arch-arm: Move AArch32 IMPLEMENTATION DEFINED registers | Giacomo Travaglini |
| 2019-01-22 | sim-se: add syscalls related to polling | Brandon Potter |
| 2019-01-16 | arch: Make the ISA register types aliases for the global types. | Gabe Black |
| 2019-01-16 | arm: Make the fp register types 64 bits. | Gabe Black |
| 2019-01-16 | arch-arm: Read VMPIDR instead of MPIDR when EL2 is Enabled | Giacomo Travaglini |
| 2019-01-16 | arch-arm: Added TLBI_ALL EL2 instruction | Anouk Van Laer |
| 2019-01-15 | arch-arm: Fix usage of RegId constructor for VecElem | Giacomo Travaglini |
| 2019-01-14 | arm: Stop using the FloatReg and FloatRegBits types. | Gabe Black |
| 2019-01-10 | sim-se, arch-arm: Add support for getdents64 | Javier Setoain |
| 2019-01-10 | arch-arm, sim-se: Add support for TLS in clone | Andreas Sandberg |
| 2019-01-10 | arch-arm, sim-se: Fix incorrect SP handling in clone | Andreas Sandberg |
| 2019-01-10 | sim-se: Refactor clone to avoid most ifdefs | Andreas Sandberg |
| 2019-01-10 | arch-arm, sim-se: Wire up syscalls needed for pthreads | Javier Setoain |
