gem5 - gem5

Age	Commit message (Collapse)	Author
2019-04-28	mem: Minimize the use of MemObject.	Gabe Black
	MemObject doesn't provide anything beyond its base ClockedObject any more, so this change removes it from most inheritance hierarchies. Occasionally MemObject is replaced with SimObject when I was fairly confident that the extra functionality of ClockedObject wasn't needed. Change-Id: Ic014ab61e56402e62548e8c831eb16e26523fdce Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18289 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-23	python: Enforce absolute imports for Python 3 compatibility	Andreas Sandberg
	Change-Id: Ia88d7fd472f7aed9b97df81468211384981bf6c6 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15983 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-18	arch-generic: Making base TLB class a MemObject	Ivan Pizarro
	Allow configuring a TLB hierarchy using ports Change-Id: I1f791829d4e072a9104e67eacf69a69de9543634 Reviewed-on: https://gem5-review.googlesource.com/c/14117 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2015-02-11	sim: Move the BaseTLB to src/arch/generic/	Andreas Sandberg
	The TLB-related code is generally architecture dependent and should live in the arch directory to signify that. --HG-- rename : src/sim/BaseTLB.py => src/arch/generic/BaseTLB.py rename : src/sim/tlb.cc => src/arch/generic/tlb.cc rename : src/sim/tlb.hh => src/arch/generic/tlb.hh