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path: root/src/arch/generic
AgeCommit message (Expand)Author
2020-02-01arch,base,cpu: Add some default constructors/operators explicitly.Gabe Black
2020-01-11arch: Make the generic micropc enabled PCState set nupc to 1.Gabe Black
2020-01-07arch,sim: Stop decoding the pseudo inst subfunc value.Gabe Black
2020-01-06arch,sim: Use the guest ABI mechanism with pseudo instructions.Gabe Black
2019-12-10sim,arch: Collapse the ISA specific versions of m5Syscall.Gabe Black
2019-11-18arch: Make and use endian specific versions of the mem helpers.Gabe Black
2019-10-19arch: Make a base class for Interrupts.Gabe Black
2019-10-18arch: Get rid of the unused GenericTLB.Gabe Black
2019-09-23cpu, mem: Changing AtomicOpFunctor* for unique_ptr<AtomicOpFunctor>Jordi Vaquero
2019-09-18arch, x86: Rework the debug faults and microops.Gabe Black
2019-08-28mem: Eliminate the Base(Slave|Master)Port classes.Gabe Black
2019-08-21arch-arm, cpu: fix ARM ubsan build on GCC 7.4.0Ciro Santilli
2019-08-09arch: Bump MaxVecRegLenInBytes to 4096Tony Gutierrez
2019-05-30arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code.Gabe Black
2019-05-29arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.Gabe Black
2019-04-28mem: Minimize the use of MemObject.Gabe Black
2019-03-19arch, cpu, dev, gpu, mem, sim, python: start using getPort.Gabe Black
2019-03-14arch-arm,cpu: Add initial support for Arm SVEGiacomo Gabrielli
2019-03-01mem-cache: alias to mem::getMasterPort in TLB classAndrea Mondelli
2019-02-23python: Enforce absolute imports for Python 3 compatibilityAndreas Sandberg
2019-02-18arch-generic: Making base TLB class a MemObjectIvan Pizarro
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
2019-01-25cpu, arch, arch-arm: Wire unused VecElem code in the O3 modelGiacomo Travaglini
2018-10-17arch: Include some additional headers in arch/generic/mmapped_ipr.cc.Gabe Black
2018-10-12arch: Explicitly specify the endianness in the generic mem helpers.Gabe Black
2018-10-02arch: Fix unserialization of VectorReg valueGabor Dozsa
2018-06-14arch: support issuing Atomic Mem Operation (AMO) requestsTuan Ta
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
2018-06-11misc: Substitute pointer to Request with aliased RequestPtrGiacomo Travaglini
2018-03-27arch: cpu: Make the ExtMachInst type a template argument in InstMap.Gabe Black
2017-12-22arch,cpu: "virtualize" the TLB interface.Gabe Black
2017-12-13arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.Gabe Black
2017-12-04misc: Rename misc.(hh|cc) to logging.(hh|cc)Gabe Black
2017-10-13mem: Signal the local monitor when clearing the global monitorNikos Nikoleris
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
2017-07-05arch: added generic vector registerRekai Gonzalez-Alberquilla
2017-07-05arch, cpu: Architectural Register structural indexingNathanael Premillieu
2017-06-22arm,sim: fix context switch stats dumps for ARM64/LinuxPaul Rosenfeld
2017-02-27syscall_emul: [PATCH 15/22] add clone/execve for threading and multiprocess s...Brandon Potter
2017-02-27arch: Include generated decoder header after normal headersAndreas Sandberg
2016-11-09style: [patch 1/22] use /r/3648/ to reorganize includesBrandon Potter
2016-08-15cpu, arch: fix the type used for the request flagsNikos Nikoleris
2016-02-06style: fix missing spaces in control statementsSteve Reinhardt
2016-01-17cpu. arch: add initiateMemRead() to ExecContext interfaceSteve Reinhardt
2016-01-17arch: don't call *Timing functions from *Atomic versionsSteve Reinhardt
2015-10-12misc: Add explicit overrides and fix other clang >= 3.5 issuesAndreas Hansson
2015-10-12misc: Remove redundant compiler-specific definesAndreas Hansson
2015-07-07sim: Refactor the serialization base classAndreas Sandberg
2015-04-29arch, base, dev, kern, sym: FreeBSD supportRuslan Bukin
2015-02-11sim: Move the BaseTLB to src/arch/generic/Andreas Sandberg