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path: root/src/arch/isa_parser.py
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2011-03-24ISA parser: Set up op_src_decl and op_dest_decl for pc operands.Gabe Black
2011-01-07scons: show sources and targets when building, and colorize output.Steve Reinhardt
I like the brevity of Ali's recent change, but the ambiguity of sometimes showing the source and sometimes the target is a little confusing. This patch makes scons typically list all sources and all targets for each action, with the common path prefix factored out for brevity. It's a little more verbose now but also more informative. Somehow Ali talked me into adding colors too, which is a whole 'nother story.
2010-12-07ISA: Get the parser to support pc state components more elegantly.Gabe Black
2010-11-15SCons: Cleanup SCons output during compileAli Saidi
2010-10-31ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.Gabe Black
This change is a low level and pervasive reorganization of how PCs are managed in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about, the PC and the NPC, and the lsb of the PC signaled whether or not you were in PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next micropc, x86 and ARM introduced variable length instruction sets, and ARM started to keep track of mode bits in the PC. Each CPU model handled PCs in its own custom way that needed to be updated individually to handle the new dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack, the complexity could be hidden in the ISA at the ISA implementation's expense. Areas like the branch predictor hadn't been updated to handle branch delay slots or micropcs, and it turns out that had introduced a significant (10s of percent) performance bug in SPARC and to a lesser extend MIPS. Rather than perpetuate the problem by reworking O3 again to handle the PC features needed by x86, this change was introduced to rework PC handling in a more modular, transparent, and hopefully efficient way. PC type: Rather than having the superset of all possible elements of PC state declared in each of the CPU models, each ISA defines its own PCState type which has exactly the elements it needs. A cross product of canned PCState classes are defined in the new "generic" ISA directory for ISAs with/without delay slots and microcode. These are either typedef-ed or subclassed by each ISA. To read or write this structure through a *Context, you use the new pcState() accessor which reads or writes depending on whether it has an argument. If you just want the address of the current or next instruction or the current micro PC, you can get those through read-only accessors on either the PCState type or the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the move away from readPC. That name is ambiguous since it's not clear whether or not it should be the actual address to fetch from, or if it should have extra bits in it like the PAL mode bit. Each class is free to define its own functions to get at whatever values it needs however it needs to to be used in ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the PC and into a separate field like ARM. These types can be reset to a particular pc (where npc = pc + sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as appropriate), printed, serialized, and compared. There is a branching() function which encapsulates code in the CPU models that checked if an instruction branched or not. Exactly what that means in the context of branch delay slots which can skip an instruction when not taken is ambiguous, and ideally this function and its uses can be eliminated. PCStates also generally know how to advance themselves in various ways depending on if they point at an instruction, a microop, or the last microop of a macroop. More on that later. Ideally, accessing all the PCs at once when setting them will improve performance of M5 even though more data needs to be moved around. This is because often all the PCs need to be manipulated together, and by getting them all at once you avoid multiple function calls. Also, the PCs of a particular thread will have spatial locality in the cache. Previously they were grouped by element in arrays which spread out accesses. Advancing the PC: The PCs were previously managed entirely by the CPU which had to know about PC semantics, try to figure out which dimension to increment the PC in, what to set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction with the PC type itself. Because most of the information about how to increment the PC (mainly what type of instruction it refers to) is contained in the instruction object, a new advancePC virtual function was added to the StaticInst class. Subclasses provide an implementation that moves around the right element of the PC with a minimal amount of decision making. In ISAs like Alpha, the instructions always simply assign NPC to PC without having to worry about micropcs, nnpcs, etc. The added cost of a virtual function call should be outweighed by not having to figure out as much about what to do with the PCs and mucking around with the extra elements. One drawback of making the StaticInsts advance the PC is that you have to actually have one to advance the PC. This would, superficially, seem to require decoding an instruction before fetch could advance. This is, as far as I can tell, realistic. fetch would advance through memory addresses, not PCs, perhaps predicting new memory addresses using existing ones. More sophisticated decisions about control flow would be made later on, after the instruction was decoded, and handed back to fetch. If branching needs to happen, some amount of decoding needs to happen to see that it's a branch, what the target is, etc. This could get a little more complicated if that gets done by the predecoder, but I'm choosing to ignore that for now. Variable length instructions: To handle variable length instructions in x86 and ARM, the predecoder now takes in the current PC by reference to the getExtMachInst function. It can modify the PC however it needs to (by setting NPC to be the PC + instruction length, for instance). This could be improved since the CPU doesn't know if the PC was modified and always has to write it back. ISA parser: To support the new API, all PC related operand types were removed from the parser and replaced with a PCState type. There are two warts on this implementation. First, as with all the other operand types, the PCState still has to have a valid operand type even though it doesn't use it. Second, using syntax like PCS.npc(target) doesn't work for two reasons, this looks like the syntax for operand type overriding, and the parser can't figure out if you're reading or writing. Instructions that use the PCS operand (which I've consistently called it) need to first read it into a local variable, manipulate it, and then write it back out. Return address stack: The return address stack needed a little extra help because, in the presence of branch delay slots, it has to merge together elements of the return PC and the call PC. To handle that, a buildRetPC utility function was added. There are basically only two versions in all the ISAs, but it didn't seem short enough to put into the generic ISA directory. Also, the branch predictor code in O3 and InOrder were adjusted so that they always store the PC of the actual call instruction in the RAS, not the next PC. If the call instruction is a microop, the next PC refers to the next microop in the same macroop which is probably not desirable. The buildRetPC function advances the PC intelligently to the next macroop (in an ISA specific way) so that that case works. Change in stats: There were no change in stats except in MIPS and SPARC in the O3 model. MIPS runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could likely be improved further by setting call/return instruction flags and taking advantage of the RAS. TODO: Add != operators to the PCState classes, defined trivially to be !(a==b). Smooth out places where PCs are split apart, passed around, and put back together later. I think this might happen in SPARC's fault code. Add ISA specific constructors that allow setting PC elements without calling a bunch of accessors. Try to eliminate the need for the branching() function. Factor out Alpha's PAL mode pc bit into a separate flag field, and eliminate places where it's blindly masked out or tested in the PC.
2010-06-02ARM: Fix custom writer/reader code for non indexed operands.Gabe Black
2010-02-26isa_parser: move the operand map stuff into the ISAParser class.Nathan Binkert
2010-02-26isa_parser: move more support functions into the ISAParser classNathan Binkert
2010-02-26isa_parser: move more stuff into the ISAParser classNathan Binkert
2010-02-26isa_parser: move the formatMap and exportContext into the ISAParser classNathan Binkert
2010-02-26isa_parser: Make stack objects class members instead of globalsNathan Binkert
2010-02-26isa_parser: add a debug variable that changes how errors are reported.Nathan Binkert
This allows us to get tracebacks in certain cases where they're more useful than our error message.
2010-02-26isa_parser: Use an exception to flag errorNathan Binkert
This allows the error to propagate more easily
2010-02-26isa_parser: Move more stuff into the ISAParser classNathan Binkert
2010-02-26isa_parser: move code around to prepare for putting more stuff in the classNathan Binkert
2010-02-26isa_parser: simple fixes, formatting and styleNathan Binkert
2009-11-05isa_parser: allow negative integer literalsNathan Binkert
2009-11-08compile: wrap 64bit numbers with ULL() so 32bit compiles workNathan Binkert
In the isa_parser, we need to check case statements.
2009-10-27POWER: Add support for the Power ISATimothy M. Jones
This adds support for the 32-bit, big endian Power ISA. This supports both integer and floating point instructions based on the Power ISA Book I v2.06.
2009-09-23isa_parser: Turn the ISA Parser into a subclass of Grammar.Nathan Binkert
This is to prepare for future cleanup where we allow SCons to create a separate grammar class for each ISA
2009-09-22scons: add slicc and ply to sys.path and PYTHONPATH so everyone has accessNathan Binkert
2009-07-20isa_parser: Get rid of the now unused ControlBitfieldOperand.Gabe Black
2009-07-10ISAs: Get rid of the IControl operand type.Gabe Black
A separate operand type is not necessary to use two bitfields to generate the index.
2009-07-08Registers: Get rid of the float register width parameter.Gabe Black
2009-07-08ISA parser: Allow alternative read/write code for operands.Gabe Black
2009-05-12isa-parser: made a few changes, but not author-worthyKorey Sewell
2008-09-10style: Remove non-leading tabs everywhere they shouldn't be. Developers ↵Ali Saidi
should configure their editors to not insert tabs
2007-11-15Get MIPS simple regression working. Take out unecessary functions ↵Korey Sewell
"setShadowSet", "CacheOp" --HG-- extra : convert_revision : a9ae8a7e62c27c2db16fd3cfa7a7f0bf5f0bf8ea
2007-11-13Add in files from merge-bare-iron, get them compiling in FS and SE modeKorey Sewell
--HG-- extra : convert_revision : d4e19afda897bc3797868b40469ce2ec7ec7d251
2007-08-07X86: Make a microcode branch microop.Gabe Black
Also some touch up for ruflag. --HG-- extra : convert_revision : 829947169af25ca6573f53b9430707101c75cc23
2007-07-20Fixed line number accountingGabe Black
--HG-- extra : convert_revision : 4c046493b98ce4a766c2121710d70650cb6a801e
2007-06-22FINISH off merge of mips mt/dsp isa extensions by adding the ↵Korey Sewell
ControlBitfieldOPerand to ISA Parser. Now, while things do build, we have to fix broken functionality... src/arch/isa_parser.py: add back deleted writeback in Control Operand --HG-- extra : convert_revision : dba11af220a1281fa53f79d87e4f8752bdfc56db
2007-06-22add Control Bitfield classKorey Sewell
--HG-- extra : convert_revision : 31e7243c8820cb9f6744c53c417460dee9adaf44
2007-05-25Merge zizzer.eecs.umich.edu:/bk/newmemGabe Black
into doughnut.mwconnections.com:/home/gblack/m5/newmem-x86 --HG-- extra : convert_revision : 276d00a73b1834d5262129c3f7e0f7fae18e23bc
2007-05-25Make the lexer and parser use objects and not the last lexer and parser ↵Gabe Black
generated. --HG-- extra : convert_revision : e751969973599cde711f9d4de0dc4772dda651ed
2007-05-24Update to ply 2.3Nathan Binkert
ext/ply/ply/lex.py: ext/ply/ply/yacc.py: ext/ply/CHANGES: ext/ply/README: ext/ply/TODO: ext/ply/doc/ply.html: ext/ply/example/ansic/clex.py: ext/ply/example/ansic/cparse.py: ext/ply/example/calc/calc.py: ext/ply/example/hedit/hedit.py: ext/ply/example/optcalc/calc.py: ext/ply/test/README: ext/ply/test/calclex.py: ext/ply/test/lex_doc1.exp: ext/ply/test/lex_doc1.py: ext/ply/test/lex_dup1.exp: ext/ply/test/lex_dup1.py: ext/ply/test/lex_dup2.exp: ext/ply/test/lex_dup2.py: ext/ply/test/lex_dup3.exp: ext/ply/test/lex_dup3.py: ext/ply/test/lex_empty.py: ext/ply/test/lex_error1.py: ext/ply/test/lex_error2.py: ext/ply/test/lex_error3.exp: ext/ply/test/lex_error3.py: ext/ply/test/lex_error4.exp: ext/ply/test/lex_error4.py: ext/ply/test/lex_hedit.exp: ext/ply/test/lex_hedit.py: ext/ply/test/lex_ignore.exp: ext/ply/test/lex_ignore.py: ext/ply/test/lex_re1.exp: ext/ply/test/lex_re1.py: ext/ply/test/lex_rule1.py: ext/ply/test/lex_token1.py: ext/ply/test/lex_token2.py: ext/ply/test/lex_token3.py: ext/ply/test/lex_token4.py: ext/ply/test/lex_token5.exp: ext/ply/test/lex_token5.py: ext/ply/test/yacc_badargs.exp: ext/ply/test/yacc_badargs.py: ext/ply/test/yacc_badprec.exp: ext/ply/test/yacc_badprec.py: ext/ply/test/yacc_badprec2.exp: ext/ply/test/yacc_badprec2.py: ext/ply/test/yacc_badrule.exp: ext/ply/test/yacc_badrule.py: ext/ply/test/yacc_badtok.exp: ext/ply/test/yacc_badtok.py: ext/ply/test/yacc_dup.exp: ext/ply/test/yacc_dup.py: ext/ply/test/yacc_error1.exp: ext/ply/test/yacc_error1.py: ext/ply/test/yacc_error2.exp: ext/ply/test/yacc_error2.py: ext/ply/test/yacc_error3.exp: ext/ply/test/yacc_error3.py: ext/ply/test/yacc_inf.exp: ext/ply/test/yacc_inf.py: ext/ply/test/yacc_missing1.exp: ext/ply/test/yacc_missing1.py: ext/ply/test/yacc_nodoc.exp: ext/ply/test/yacc_nodoc.py: ext/ply/test/yacc_noerror.exp: ext/ply/test/yacc_noerror.py: ext/ply/test/yacc_nop.exp: ext/ply/test/yacc_nop.py: ext/ply/test/yacc_notfunc.exp: ext/ply/test/yacc_notfunc.py: ext/ply/test/yacc_notok.exp: ext/ply/test/yacc_notok.py: ext/ply/test/yacc_rr.exp: ext/ply/test/yacc_rr.py: ext/ply/test/yacc_simple.exp: ext/ply/test/yacc_simple.py: ext/ply/test/yacc_sr.exp: ext/ply/test/yacc_sr.py: ext/ply/test/yacc_term1.exp: ext/ply/test/yacc_term1.py: ext/ply/test/yacc_unused.exp: ext/ply/test/yacc_unused.py: ext/ply/test/yacc_uprec.exp: ext/ply/test/yacc_uprec.py: Import patch ply.diff src/arch/isa_parser.py: everything is now within the ply package --HG-- rename : ext/ply/lex.py => ext/ply/ply/lex.py rename : ext/ply/yacc.py => ext/ply/ply/yacc.py extra : convert_revision : fca8deabd5c095bdeabd52a1f236ae1404ef106e
2007-04-04Fix a regular expression problem when recognizing labels for string ↵Gabe Black
substitution. --HG-- extra : convert_revision : ba398e1b434efda28882f159d5a4419302276371
2007-04-04Make "Name" really be the same as "name" with only the first letter ↵Gabe Black
capitalized. Before, it had the first letter capitalized but all the others lower case --HG-- extra : convert_revision : bcbb28f2bf268765c1d37075a4417a4a6c1b9588
2007-03-29Allow "let" blocks to add code to the output files.Gabe Black
--HG-- extra : convert_revision : 0ffddb2b40dccbf2a3790464c843cfc1b43eaa02
2007-03-22Add structure based bitfield syntax to the isa_parser. This is primarily ↵Gabe Black
useful for x86. --HG-- extra : convert_revision : dfe6df160d00adec1830d9b88520ba20834d1209
2007-03-20Added syntax for structure oriented extMachInsts.Gabe Black
--HG-- extra : convert_revision : 4a30c58019ad8e3dd8dffb4c4c08eb6914e5c5be
2007-03-07I missed a couple of WithEffects, this should do itAli Saidi
--HG-- extra : convert_revision : 19fce78a19b27b7ccb5e3653a64b46e6d5292915
2007-03-02make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way ↵Ali Saidi
as the twin 64 bit loads src/arch/isa_parser.py: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/operands.isa: src/base/bigint.hh: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: src/mem/packet_access.hh: make ldtw(a) Twin 32 bit load work correctly --HG-- extra : convert_revision : 2646b269d58cc1774e896065875a56cf5e313b42
2007-02-12rename store conditional stuff as extra data so it can be used for ↵Ali Saidi
conditional swaps as well Add support for a twin 64 bit int load Add Memory barrier and write barrier flags as appropriate Make atomic memory ops atomic src/arch/alpha/isa/mem.isa: src/arch/alpha/locked_mem.hh: src/cpu/base_dyn_inst.hh: src/mem/cache/cache_blk.hh: src/mem/cache/cache_impl.hh: rename store conditional stuff as extra data so it can be used for conditional swaps as well src/arch/alpha/types.hh: src/arch/mips/types.hh: src/arch/sparc/types.hh: add a largest read data type for statically allocating read buffers in atomic simple cpu src/arch/isa_parser.py: Add support for a twin 64 bit int load src/arch/sparc/isa/decoder.isa: Make atomic memory ops atomic Add Memory barrier and write barrier flags as appropriate src/arch/sparc/isa/formats/mem/basicmem.isa: add post access code block and define a twinload format for twin loads src/arch/sparc/isa/formats/mem/blockmem.isa: remove old microcoded twin load coad src/arch/sparc/isa/formats/mem/mem.isa: swap.isa replaces the code in loadstore.isa src/arch/sparc/isa/formats/mem/util.isa: add a post access code block src/arch/sparc/isa/includes.isa: need bigint.hh for Twin64_t src/arch/sparc/isa/operands.isa: add a twin 64 int type src/cpu/simple/atomic.cc: src/cpu/simple/atomic.hh: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: add support for twinloads add support for swap and conditional swap instructions rename store conditional stuff as extra data so it can be used for conditional swaps as well src/mem/packet.cc: src/mem/packet.hh: Add support for atomic swap memory commands src/mem/packet_access.hh: Add endian conversion function for Twin64_t type src/mem/physical.cc: src/mem/physical.hh: src/mem/request.hh: Add support for atomic swap memory commands Rename sc code to extradata --HG-- extra : convert_revision : 69d908512fb34a4e28b29a6e58b807fb1a6b1656
2006-12-17Minor cleanup of new snippet/subst code.Steve Reinhardt
--HG-- extra : convert_revision : d81e0d1356f3433e8467e407d66d4afb95614748
2006-12-17Convert Alpha (and finish converting MIPS) to newSteve Reinhardt
InstObjParam interface. src/arch/alpha/isa/branch.isa: src/arch/alpha/isa/fp.isa: src/arch/alpha/isa/int.isa: src/arch/alpha/isa/main.isa: src/arch/alpha/isa/mem.isa: src/arch/alpha/isa/pal.isa: src/arch/mips/isa/formats/mem.isa: src/arch/mips/isa/formats/util.isa: Get rid of CodeBlock calls to adapt to new InstObjParam interface. src/arch/isa_parser.py: Check template code for operands (in addition to snippets). src/cpu/o3/alpha/dyn_inst.hh: Add (read|write)MiscRegOperand calls to Alpha DynInst. --HG-- extra : convert_revision : 332caf1bee19b014cb62c1ed9e793e793334c8ee
2006-12-17Compilation fix after messy merge.Gabe Black
--HG-- extra : convert_revision : bf650dfe401377ce1b4c952aa8bfe3708c865472
2006-12-16Merge zizzer:/bk/newmemGabe Black
into zower.eecs.umich.edu:/eecshome/m5/newmem src/arch/isa_parser.py: src/arch/sparc/isa/formats/mem/basicmem.isa: src/arch/sparc/isa/formats/mem/blockmem.isa: src/arch/sparc/isa/formats/mem/util.isa: src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: src/cpu/o3/iew_impl.hh: Hand Merge --HG-- extra : convert_revision : ae1b25cde85ab8ec275a09d554acd372887d4d47
2006-12-16Changes to the isa_parser and affected files to fix an indexing problem with ↵Gabe Black
split execute instructions and miscregs aliasing with integer registers. src/arch/isa_parser.py: Rearranged things so that classes with more than one execute function treat operands properly. 1. Eliminated the CodeBlock class 2. Created a SubOperandList 3. Redefined how InstObjParams is constructed To define an InstObjParam, you can either pass in a single code literal which will be named "code", or you can pass in a dictionary of code snippets which will be substituted into the Templates. In order to get this to work, there is a new restriction that each template has only one function in it. These changes should only affect memory instructions which have regular and split execute functions. Also changed the MiscRegs so that they use the instrunctions srcReg and destReg arrays. src/arch/sparc/isa/formats/basic.isa: src/arch/sparc/isa/formats/branch.isa: src/arch/sparc/isa/formats/integerop.isa: src/arch/sparc/isa/formats/mem/basicmem.isa: src/arch/sparc/isa/formats/mem/blockmem.isa: src/arch/sparc/isa/formats/mem/util.isa: src/arch/sparc/isa/formats/nop.isa: src/arch/sparc/isa/formats/priv.isa: src/arch/sparc/isa/formats/trap.isa: Rearranged to work with new InstObjParam scheme. src/cpu/o3/sparc/dyn_inst.hh: Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. Also changed the names of the other accessors so that they have the suffix "Operand" if they use those arrays. src/cpu/simple/base.hh: Added functions to access the miscregs using the indexes from instructions srcReg and destReg arrays. --HG-- extra : convert_revision : c91e1073138b72bcf4113a721e0ed40ec600cf2e
2006-12-15Merge zizzer:/bk/sparcfsLisa Hsu
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem --HG-- extra : convert_revision : 92a865a90a7c3e251ed1443f79640f761b359c1d