gem5 - gem5

Age	Commit message (Collapse)	Author
2017-07-12	mips, x86: Refactor some Event subclasses into lambdas	Sean Wilson
	Change-Id: I09570e569efe55f5502bc201e03456738999e714 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3920 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2016-11-09	style: [patch 1/22] use /r/3648/ to reorganize includes	Brandon Potter

2016-02-06	style: fix missing spaces in control statements	Steve Reinhardt
	Result of running 'hg m5style --skip-all --fix-control -a'.
2015-02-16	arch: Make readMiscRegNoEffect const throughout	Andreas Hansson
	Finally took the plunge and made this apply to all ISAs, not just ARM.
2014-01-24	arch, cpu: Add support for flattening misc register indexes.	Ali Saidi
	With ARMv8 support the same misc register id results in accessing different registers depending on the current mode of the processor. This patch adds the same orthogonality to the misc register file as the others (int, float, cc). For all the othre ISAs this is currently a null-implementation. Additionally, a system variable is added to all the ISA objects.
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
	The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers. This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU.
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
	This patch addresses the comments and feedback on the preceding patch that reworks the clocks and now more clearly shows where cycles (relative cycle counts) are used to express time. Instead of bumping the existing patch I chose to make this a separate patch, merely to try and focus the discussion around a smaller set of changes. The two patches will be pushed together though. This changes done as part of this patch are mostly following directly from the introduction of the wrapper class, and change enough code to make things compile and run again. There are definitely more places where int/uint/Tick is still used to represent cycles, and it will take some time to chase them all down. Similarly, a lot of parameters should be changed from Param.Tick and Param.Unsigned to Param.Cycles. In addition, the use of curTick is questionable as there should not be an absolute cycle. Potential solutions can be built on top of this patch. There is a similar situation in the o3 CPU where lastRunningCycle is currently counting in Cycles, and is still an absolute time. More discussion to be had in other words. An additional change that would be appropriate in the future is to perform a similar wrapping of Tick and probably also introduce a Ticks class along with suitable operators for all these classes.
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
	At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
2011-04-15	includes: sort all includes	Nathan Binkert

2011-03-26	mips: cleanup ISA-specific code	Korey Sewell
	*** (1): get rid of expandForMT function MIPS is the only ISA that cares about having a piece of ISA state integrate multiple threads so add constants for MIPS and relieve the other ISAs from having to define this. Also, InOrder was the only core that was actively calling this function * * * (2): get rid of corespecific type The CoreSpecific type was used as a proxy to pass in HW specific params to a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense to not force every other ISA to use CoreSpecific as well use a special reset function to set it. That probably should go in a PowerOn reset fault anyway.
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
	This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values.
2009-12-31	MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg.	Gabe Black
	The MIPS ISA object expects to be constructed with a CPU pointer it uses to look at other thread contexts and allow them to be manipulated with control registers. Unfortunately, that differs from all the other ISA classes and would complicate their implementation. This change makes the event constructor use a CPU pointer pulled out of the thread context passed to setMiscReg instead.
2009-07-21	MIPS: Format the register index constants like the other ISAs.	Gabe Black
	Also a few more style fixes.
2009-07-21	MIPS: Many style fixes.	Gabe Black
	White space, commented out code, some other minor fixes.
2009-07-20	MIPS: Use BitUnions instead of bits() functions and constants.	Gabe Black
	Also fix style issues in regions around these changes.
2009-07-09	MIPS: Fold the MiscRegFile all the way into the ISA object.	Gabe Black

2009-07-08	Registers: Collapse ARM and MIPS regfile directories.	Gabe Black
	--HG-- rename : src/arch/arm/regfile/misc_regfile.hh => src/arch/arm/misc_regfile.hh rename : src/arch/arm/regfile/regfile.cc => src/arch/arm/regfile.cc rename : src/arch/mips/regfile/misc_regfile.cc => src/arch/mips/misc_regfile.cc rename : src/arch/mips/regfile/misc_regfile.hh => src/arch/mips/misc_regfile.hh
2009-07-08	Registers: Add an ISA object which replaces the MiscRegFile.	Gabe Black
	This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.