gem5 - gem5

Age	Commit message (Collapse)	Author
2009-12-31	MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg.	Gabe Black
	The MIPS ISA object expects to be constructed with a CPU pointer it uses to look at other thread contexts and allow them to be manipulated with control registers. Unfortunately, that differs from all the other ISA classes and would complicate their implementation. This change makes the event constructor use a CPU pointer pulled out of the thread context passed to setMiscReg instead.
2009-07-21	MIPS: Format the register index constants like the other ISAs.	Gabe Black
	Also a few more style fixes.
2009-07-21	MIPS: Many style fixes.	Gabe Black
	White space, commented out code, some other minor fixes.
2009-07-20	MIPS: Use BitUnions instead of bits() functions and constants.	Gabe Black
	Also fix style issues in regions around these changes.
2009-07-09	MIPS: Fold the MiscRegFile all the way into the ISA object.	Gabe Black

2009-07-08	Registers: Collapse ARM and MIPS regfile directories.	Gabe Black
	--HG-- rename : src/arch/arm/regfile/misc_regfile.hh => src/arch/arm/misc_regfile.hh rename : src/arch/arm/regfile/regfile.cc => src/arch/arm/regfile.cc rename : src/arch/mips/regfile/misc_regfile.cc => src/arch/mips/misc_regfile.cc rename : src/arch/mips/regfile/misc_regfile.hh => src/arch/mips/misc_regfile.hh
2009-07-08	Registers: Add an ISA object which replaces the MiscRegFile.	Gabe Black
	This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.