gem5 - gem5

Age	Commit message (Expand)	Author
2017-07-12	mips, x86: Refactor some Event subclasses into lambdas	Sean Wilson
2016-11-09	style: [patch 1/22] use /r/3648/ to reorganize includes	Brandon Potter
2016-02-06	style: fix missing spaces in control statements	Steve Reinhardt
2015-02-16	arch: Make readMiscRegNoEffect const throughout	Andreas Hansson
2014-01-24	arch, cpu: Add support for flattening misc register indexes.	Ali Saidi
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
2012-08-28	Clock: Add a Cycles wrapper class and use where applicable	Andreas Hansson
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-04-15	includes: sort all includes	Nathan Binkert
2011-03-26	mips: cleanup ISA-specific code	Korey Sewell
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
2009-12-31	MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg.	Gabe Black
2009-07-21	MIPS: Format the register index constants like the other ISAs.	Gabe Black
2009-07-21	MIPS: Many style fixes.	Gabe Black
2009-07-20	MIPS: Use BitUnions instead of bits() functions and constants.	Gabe Black
2009-07-09	MIPS: Fold the MiscRegFile all the way into the ISA object.	Gabe Black
2009-07-08	Registers: Collapse ARM and MIPS regfile directories.	Gabe Black
2009-07-08	Registers: Add an ISA object which replaces the MiscRegFile.	Gabe Black