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2017-07-12mips, x86: Refactor some Event subclasses into lambdasSean Wilson
Change-Id: I09570e569efe55f5502bc201e03456738999e714 Signed-off-by: Sean Wilson <spwilson2@wisc.edu> Reviewed-on: https://gem5-review.googlesource.com/3920 Maintainer: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2017-07-05cpu: Added interface for vector reg fileRekai Gonzalez-Alberquilla
This patch adds some more functionality to the cpu model and the arch to interface with the vector register file. This change consists mainly of augmenting ThreadContexts and ExecContexts with calls to get/set full vectors, underlying microarchitectural elements or lanes. Those are meant to interface with the vector register file. All classes that implement this interface also get an appropriate implementation. This requires implementing the vector register file for the different models using the VecRegContainer class. This change set also updates the Result abstraction to contemplate the possibility of having a vector as result. The changes also affect how the remote_gdb connection works. There are some (nasty) side effects, such as the need to define dummy numPhysVecRegs parameter values for architectures that do not implement vector extensions. Nathanael Premillieu's work with an increasing number of fixes and improvements of mine. Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues and CC reg free list initialisation ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2705
2017-07-05cpu: Simplify the rename interface and use RegIdRekai Gonzalez-Alberquilla
With the hierarchical RegId there are a lot of functions that are redundant now. The idea behind the simplification is that instead of having the regId, telling which kind of register read/write/rename/lookup/etc. and then the function panic_if'ing if the regId is not of the appropriate type, we provide an interface that decides what kind of register to read depending on the register type of the given regId. Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> [ Fix RISCV build issues ] Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/2702
2015-07-28revert 5af8f40d8f2cNilay Vaish
2015-07-26cpu: implements vector registersNilay Vaish
This adds a vector register type. The type is defined as a std::array of a fixed number of uint64_ts. The isa_parser.py has been modified to parse vector register operands and generate the required code. Different cpus have vector register files now.
2015-02-16arch: Make readMiscRegNoEffect const throughoutAndreas Hansson
Finally took the plunge and made this apply to all ISAs, not just ARM.
2014-10-16arch: Use shared_ptr for all FaultsAndreas Hansson
This patch takes quite a large step in transitioning from the ad-hoc RefCountingPtr to the c++11 shared_ptr by adopting its use for all Faults. There are no changes in behaviour, and the code modifications are mostly just replacing "new" with "make_shared".
2014-01-24arch: Make all register index flattening constAndreas Hansson
This patch makes all the register index flattening methods const for all the ISAs. As part of this, readMiscRegNoEffect for ARM is also made const.
2014-01-24arch, cpu: Add support for flattening misc register indexes.Ali Saidi
With ARMv8 support the same misc register id results in accessing different registers depending on the current mode of the processor. This patch adds the same orthogonality to the misc register file as the others (int, float, cc). For all the othre ISAs this is currently a null-implementation. Additionally, a system variable is added to all the ISA objects.
2013-10-15cpu: add a condition-code register classYasuko Eckert
Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
2013-02-19scons: Add warning for overloaded virtual functionsAndreas Hansson
Fix the ISA startup warnings
2013-01-12x86: Changes to decoder, corrects 9376Nilay Vaish
The changes made by the changeset 9376 were not quite correct. The patch made changes to the code which resulted in decoder not getting initialized correctly when the state was restored from a checkpoint. This patch adds a startup function to each ISA object. For x86, this function sets the required state in the decoder. For other ISAs, the function is empty right now.
2013-01-07arch: Move the ISA object to a separate sectionAndreas Sandberg
After making the ISA an independent SimObject, it is serialized automatically by the Python world. Previously, this just resulted in an empty ISA section. This patch moves the contents of the ISA to that section and removes the explicit ISA serialization from the thread contexts, which makes it behave like a normal SimObject during serialization. Note: This patch breaks checkpoint backwards compatibility! Use the cpt_upgrader.py utility to upgrade old checkpoints to the new format.
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers. This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU.
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
This patch addresses the comments and feedback on the preceding patch that reworks the clocks and now more clearly shows where cycles (relative cycle counts) are used to express time. Instead of bumping the existing patch I chose to make this a separate patch, merely to try and focus the discussion around a smaller set of changes. The two patches will be pushed together though. This changes done as part of this patch are mostly following directly from the introduction of the wrapper class, and change enough code to make things compile and run again. There are definitely more places where int/uint/Tick is still used to represent cycles, and it will take some time to chase them all down. Similarly, a lot of parameters should be changed from Param.Tick and Param.Unsigned to Param.Cycles. In addition, the use of curTick is questionable as there should not be an absolute cycle. Potential solutions can be built on top of this patch. There is a similar situation in the o3 CPU where lastRunningCycle is currently counting in Cycles, and is still an absolute time. More discussion to be had in other words. An additional change that would be appropriate in the future is to perform a similar wrapping of Tick and probably also introduce a Ticks class along with suitable operators for all these classes.
2011-04-15includes: sort all includesNathan Binkert
2011-03-26mips: cleanup ISA-specific codeKorey Sewell
*** (1): get rid of expandForMT function MIPS is the only ISA that cares about having a piece of ISA state integrate multiple threads so add constants for MIPS and relieve the other ISAs from having to define this. Also, InOrder was the only core that was actively calling this function * * * (2): get rid of corespecific type The CoreSpecific type was used as a proxy to pass in HW specific params to a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense to not force every other ISA to use CoreSpecific as well use a special reset function to set it. That probably should go in a PowerOn reset fault anyway.
2011-02-03Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.Gabe Black
--HG-- rename : src/sim/fault.hh => src/sim/fault_fwd.hh
2010-09-13Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.Gabe Black
Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense.
2009-12-31MIPS: Extract CPU pointer from the thread context in scheduleCP0 setMiscReg.Gabe Black
The MIPS ISA object expects to be constructed with a CPU pointer it uses to look at other thread contexts and allow them to be manipulated with control registers. Unfortunately, that differs from all the other ISA classes and would complicate their implementation. This change makes the event constructor use a CPU pointer pulled out of the thread context passed to setMiscReg instead.
2009-10-17ISA: Fix compilation.Gabe Black
2009-07-09MIPS: Fold the MiscRegFile all the way into the ISA object.Gabe Black
2009-07-08Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.Gabe Black
2009-07-08Registers: Collapse ARM and MIPS regfile directories.Gabe Black
--HG-- rename : src/arch/arm/regfile/misc_regfile.hh => src/arch/arm/misc_regfile.hh rename : src/arch/arm/regfile/regfile.cc => src/arch/arm/regfile.cc rename : src/arch/mips/regfile/misc_regfile.cc => src/arch/mips/misc_regfile.cc rename : src/arch/mips/regfile/misc_regfile.hh => src/arch/mips/misc_regfile.hh
2009-07-08Registers: Add an ISA object which replaces the MiscRegFile.Gabe Black
This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.