gem5 - gem5

Age	Commit message (Expand)	Author
2014-12-02	cpu: Always mask the snoop address when performing lock check	Andreas Hansson
2014-01-24	cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...	Ali Saidi
2013-01-07	o3: Fix issue with LLSC ordering and speculation	Ali Saidi
2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
2011-01-07	Replace curTick global variable with accessor functions.	Steve Reinhardt
2010-12-07	O3: Make all instructions that write a misc. register not perform the write u...	Giacomo Gabrielli
2010-09-10	style: fix sorting of includes and whitespace in some files	Nathan Binkert
2009-07-31	mips: fix ll/sc pairs working incorrectly because of accidental clobber of LL...	Korey Sewell
2009-07-21	MIPS: Format the register index constants like the other ISAs.	Gabe Black
2009-07-21	MIPS: Many style fixes.	Gabe Black
2009-07-08	Registers: Add a registers.hh file as an ISA switched header.	Gabe Black
2008-11-04	get rid of all instances of readTid() and getThreadNum(). Unify and eliminate	Lisa Hsu
2008-11-02	Add in Context IDs to the simulator. From now on, cpuId is almost never used,	Lisa Hsu
2008-11-02	make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered	Lisa Hsu
2008-10-09	O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA.	Gabe Black
2007-11-15	fix MIPS headers	Korey Sewell
2007-11-13	Add in files from merge-bare-iron, get them compiling in FS and SE mode	Korey Sewell
2007-06-22	mips import pt. 1	Korey Sewell
2006-10-08	Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)	Steve Reinhardt