summaryrefslogtreecommitdiff
path: root/src/arch/mips/locked_mem.hh
AgeCommit message (Expand)Author
2016-04-07mem: Remove threadId from memory request classMitch Hayenga
2014-12-02cpu: Always mask the snoop address when performing lock checkAndreas Hansson
2014-01-24cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...Ali Saidi
2013-01-07o3: Fix issue with LLSC ordering and speculationAli Saidi
2011-04-15trace: reimplement the DTRACE function so it doesn't use a vectorNathan Binkert
2011-01-07Replace curTick global variable with accessor functions.Steve Reinhardt
2010-12-07O3: Make all instructions that write a misc. register not perform the write u...Giacomo Gabrielli
2010-09-10style: fix sorting of includes and whitespace in some filesNathan Binkert
2009-07-31mips: fix ll/sc pairs working incorrectly because of accidental clobber of LL...Korey Sewell
2009-07-21MIPS: Format the register index constants like the other ISAs.Gabe Black
2009-07-21MIPS: Many style fixes.Gabe Black
2009-07-08Registers: Add a registers.hh file as an ISA switched header.Gabe Black
2008-11-04get rid of all instances of readTid() and getThreadNum(). Unify and eliminateLisa Hsu
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
2008-11-02make BaseCPU the provider of _cpuId, and cpuId() instead of being scatteredLisa Hsu
2008-10-09O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA.Gabe Black
2007-11-15fix MIPS headersKorey Sewell
2007-11-13Add in files from merge-bare-iron, get them compiling in FS and SE modeKorey Sewell
2007-06-22mips import pt. 1Korey Sewell
2006-10-08Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)Steve Reinhardt