| Age | Commit message (Expand) | Author |
|---|---|---|
| 2017-07-05 | arch, cpu: Architectural Register structural indexing | Nathanael Premillieu |
| 2015-07-28 | revert 5af8f40d8f2c | Nilay Vaish |
| 2015-07-26 | cpu: implements vector registers | Nilay Vaish |
| 2013-10-15 | cpu: add a condition-code register class | Yasuko Eckert |
| 2013-10-15 | cpu: rename *_DepTag constants to *_Reg_Base | Steve Reinhardt |
| 2013-10-15 | isa: clean up register constants | Steve Reinhardt |
| 2012-06-05 | O3: Clean up the O3 structures and try to pack them a bit better. | Ali Saidi |
| 2012-04-23 | ISA: Put parser generated files in a "generated" directory. | Gabe Black |
| 2012-01-12 | mips: definition of MIPS64_QNAN in registers.hh | Deyuan Guo |
| 2010-08-25 | ARM: Fixed register flattening logic (FP_Base_DepTag was set too low) | Min Kyu Jeong |
| 2009-12-31 | MIPS: Create an artificial control register to hold the thread pointer. | Gabe Black |
| 2009-07-21 | MIPS: Format the register index constants like the other ISAs. | Gabe Black |
| 2009-07-08 | Registers: Add a registers.hh file as an ISA switched header. | Gabe Black |
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index : gem5 | |
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