Age | Commit message (Collapse) | Author |
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extra : convert_revision : f799b65f1b2a6bf43605e6870b0f39b473dc492b
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--HG--
extra : convert_revision : 099e380395fc1fdaef993b019d3d4e596e8076c2
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for store conditional.
--HG--
extra : convert_revision : 73efd2ca17994e0e19c08746441874a2ac8183af
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--HG--
extra : convert_revision : 9ecfd5a0a151c03503e42faf98240da12fd719b1
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conditional swaps as well
Add support for a twin 64 bit int load
Add Memory barrier and write barrier flags as appropriate
Make atomic memory ops atomic
src/arch/alpha/isa/mem.isa:
src/arch/alpha/locked_mem.hh:
src/cpu/base_dyn_inst.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/arch/alpha/types.hh:
src/arch/mips/types.hh:
src/arch/sparc/types.hh:
add a largest read data type for statically allocating read buffers in atomic simple cpu
src/arch/isa_parser.py:
Add support for a twin 64 bit int load
src/arch/sparc/isa/decoder.isa:
Make atomic memory ops atomic
Add Memory barrier and write barrier flags as appropriate
src/arch/sparc/isa/formats/mem/basicmem.isa:
add post access code block and define a twinload format for twin loads
src/arch/sparc/isa/formats/mem/blockmem.isa:
remove old microcoded twin load coad
src/arch/sparc/isa/formats/mem/mem.isa:
swap.isa replaces the code in loadstore.isa
src/arch/sparc/isa/formats/mem/util.isa:
add a post access code block
src/arch/sparc/isa/includes.isa:
need bigint.hh for Twin64_t
src/arch/sparc/isa/operands.isa:
add a twin 64 int type
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
add support for twinloads
add support for swap and conditional swap instructions
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/mem/packet.cc:
src/mem/packet.hh:
Add support for atomic swap memory commands
src/mem/packet_access.hh:
Add endian conversion function for Twin64_t type
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
Add support for atomic swap memory commands
Rename sc code to extradata
--HG--
extra : convert_revision : 69d908512fb34a4e28b29a6e58b807fb1a6b1656
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--HG--
extra : convert_revision : 007e83ab452849ce527fe252148e7a1dc423c850
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--HG--
extra : convert_revision : 2166b511c3615f7a2355f058a624e9ffe8259e65
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--HG--
extra : convert_revision : d81e0d1356f3433e8467e407d66d4afb95614748
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InstObjParam interface.
src/arch/alpha/isa/branch.isa:
src/arch/alpha/isa/fp.isa:
src/arch/alpha/isa/int.isa:
src/arch/alpha/isa/main.isa:
src/arch/alpha/isa/mem.isa:
src/arch/alpha/isa/pal.isa:
src/arch/mips/isa/formats/mem.isa:
src/arch/mips/isa/formats/util.isa:
Get rid of CodeBlock calls to adapt to new InstObjParam interface.
src/arch/isa_parser.py:
Check template code for operands (in addition to snippets).
src/cpu/o3/alpha/dyn_inst.hh:
Add (read|write)MiscRegOperand calls to Alpha DynInst.
--HG--
extra : convert_revision : 332caf1bee19b014cb62c1ed9e793e793334c8ee
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--HG--
extra : convert_revision : 2e174ecfce8c86732e1addfc23e961429b86a570
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into zower.eecs.umich.edu:/eecshome/m5/newmem
src/arch/isa_parser.py:
src/arch/sparc/isa/formats/mem/basicmem.isa:
src/arch/sparc/isa/formats/mem/blockmem.isa:
src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
src/cpu/o3/iew_impl.hh:
Hand Merge
--HG--
extra : convert_revision : ae1b25cde85ab8ec275a09d554acd372887d4d47
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into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
--HG--
extra : convert_revision : 92a865a90a7c3e251ed1443f79640f761b359c1d
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we can merge back with newmem.
exetrace.cc:
wrap this variable between FULL_SYSTEM #ifs
mmaped_ipr.hh:
fix for build
miscregfile.cc:
fixes for HPSTATE access during SE mode
src/arch/sparc/miscregfile.cc:
fixes for HPSTATE access during SE mode
src/arch/mips/mmaped_ipr.hh:
fix for build
src/cpu/exetrace.cc:
wrap this variable between FULL_SYSTEM #ifs
--HG--
extra : convert_revision : c5b9d56ab99018a91d04de47ba1d5ca7768590bb
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into zower.eecs.umich.edu:/eecshome/m5/newmem
--HG--
extra : convert_revision : 17d6c49ee15af5d192dedf82871159219d4277cd
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(read|set)(Int|Float)RegOperand to distinguish from non-StaticInst version.
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extra : convert_revision : b33ce0ebe2fee86cc791c00a35d8c6e395e1380c
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--HG--
extra : convert_revision : 618f8404ec5380615e28170d761b2fcdf9c07d96
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--HG--
extra : convert_revision : 2c32851584001734d139f36c4d58c5e61067fcfc
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miscregs into the integer register file so they get renamed.
src/arch/alpha/syscallreturn.hh:
src/arch/mips/syscallreturn.hh:
src/sim/syscallreturn.hh:
Move the SyscallReturn class into sim/syscallreturn.hh
src/arch/sparc/faults.cc:
src/arch/sparc/isa/operands.isa:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/miscregfile.cc:
src/arch/sparc/miscregfile.hh:
src/arch/sparc/process.cc:
src/arch/sparc/sparc_traits.hh:
Move some miscregs into the integer register file so they get renamed.
--HG--
extra : convert_revision : df5b94fa1e7fdca34816084e0a423d6fdf86c79b
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src/arch/SConscript:
add mmaped_ipr.hh to switch headers
src/arch/sparc/asi.hh:
make ASI_IMPLICT=0 so by default nothing needs to be done
src/arch/sparc/miscregfile.hh:
miscregfile no longer needs to include asi.hh
src/arch/sparc/tlb.cc:
src/arch/sparc/tlb.hh:
implement panic instructions for mmaped ipr reads
src/cpu/simple/atomic.cc:
add check for mmaped iprs and handle them if it exists
src/mem/request.hh:
allocate space in the flags for mmaped iprs. Put in in the first 8 bits so that by default its fast. Move the other flags up 8 bits
--HG--
extra : convert_revision : 31255b0494588c4d06a727fe35241121d741b115
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--HG--
extra : convert_revision : a2d3cf29ab65c61af27d82a8c421a41a19fd5aeb
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--HG--
extra : convert_revision : 86f5585fe9ceb2ee30836d35384ebcddc1357c2a
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file functions to not take faults
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extra : convert_revision : 1cef0734462ee2e4db12482462c2ab3c134d3675
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
--HG--
extra : convert_revision : 2711fec2bf72801999b060e65f0bf744c18734fb
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--HG--
extra : convert_revision : d9eb83ab77ffd2d725961f295b1733137e187711
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and call it packet_access.hh and fix the #includes so
things compile right.
--HG--
extra : convert_revision : d3626c9715b9f7e51bb3ab8d97e971fad4e0b724
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into zeep.eecs.umich.edu:/home/gblack/m5/newmem
--HG--
extra : convert_revision : 30b2475ba034550376455e1bc0e52e19a200fd5a
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and PhysicalMemory. *No* support for caches or O3CPU.
Note that properly setting cpu_id on all CPUs is now required
for correct operation.
src/arch/SConscript:
src/base/traceflags.py:
src/cpu/base.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
src/cpu/simple/timing.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
src/python/m5/objects/BaseCPU.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
Implement Alpha LL/SC support for SimpleCPU (Atomic & Timing)
and PhysicalMemory. *No* support for caches or O3CPU.
--HG--
extra : convert_revision : 6ce982d44924cc477e049b9adf359818908e72be
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--HG--
extra : convert_revision : e5b200e4e053702fc703f44149d18ce48ac4eaa6
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various ids as LiveProcess parameters.
src/arch/alpha/linux/process.cc:
src/arch/alpha/linux/process.hh:
src/arch/alpha/process.cc:
src/arch/alpha/process.hh:
src/arch/alpha/tru64/process.cc:
src/arch/alpha/tru64/process.hh:
src/arch/mips/linux/process.cc:
src/arch/mips/linux/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/sparc/linux/process.cc:
src/arch/sparc/linux/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
src/arch/sparc/solaris/process.cc:
src/arch/sparc/solaris/process.hh:
src/sim/process.cc:
src/sim/process.hh:
src/sim/syscall_emul.cc:
src/sim/syscall_emul.hh:
Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters.
src/kern/tru64/tru64.hh:
Changed Process to LiveProcess in syscall handlers and fixed the implementation of uid, euid, gid, egid, pid and ppid as LiveProcess parameters. Also fit tru64 in with the new way to handle stat calls.
--HG--
extra : convert_revision : 0198b838e5c09a730065dc6f018738145bc96269
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throughout CPU models
src/arch/alpha/isa_traits.hh:
src/arch/mips/isa_traits.hh:
src/arch/sparc/isa_traits.hh:
define 'ISA_HAS_DELAY_SLOT'
src/cpu/base_dyn_inst.hh:
src/cpu/o3/bpred_unit_impl.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/simple/base.cc:
use ISA_HAS_DELAY_SLOT instead of THE_ISA == ALPHA_ISA
--HG--
extra : convert_revision : 24c7460d9391e8d443c9fe08e17c331ae8e9c36a
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Nate needs to fix sinic builder stuff
Gabe needs to verify my fixes to decoder.isa
OPT/DEBUG compiles for ALPHA_FS, ALPHA_SE, MIPS_SE, SPARC_SE with this changeset
README:
Fix the swig version in the readme
src/SConscript:
remove sinic until nate fixes the builder crap for it
src/arch/alpha/system.hh:
src/arch/mips/isa/includes.isa:
src/arch/sparc/isa/decoder.isa:
src/base/stats/visit.cc:
src/base/timebuf.hh:
src/dev/ide_disk.cc:
src/dev/sinic.cc:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr_queue.cc:
src/mem/packet.hh:
src/mem/request.hh:
src/sim/builder.hh:
src/sim/system.hh:
fixes for gcc 4.1
--HG--
extra : convert_revision : 3775427c0047b282574d4831dd602c96cac3ba17
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--HG--
extra : convert_revision : 6b11e039cbc061dab75195fa1aebe6ca2cdc6f91
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src/arch/alpha/regfile.hh:
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/int_regfile.hh:
src/arch/mips/regfile/misc_regfile.hh:
src/cpu/exetrace.hh:
Added functions to start to support dumping register values once per cycle.
src/cpu/exetrace.cc:
Added some code to support printing the value of registers after each cycle.
src/python/m5/main.py:
Options to turn on output after every instruction. They are commented out.
--HG--
extra : convert_revision : 168a48a6b98ab6be412a96bdee831c71906958b0
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created a seperate file for the syscallreturn class.
--HG--
extra : convert_revision : 9507ea1c09fda959f00aec9ec8ffb887ec8dd0f9
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src/arch/mips/isa/base.isa:
special case syscall disasembly... maybe give own instruction class?
src/arch/mips/isa/decoder.isa:
add 'IsSerializeAfter' flag for syscall
src/cpu/o3/commit.hh:
Add skidBuffer to commit
src/cpu/o3/commit_impl.hh:
Use skidbuffer in MIPS ISA
src/cpu/o3/fetch_impl.hh:
Print name out when there is a fault
src/cpu/o3/mips/cpu_impl.hh:
change comment
--HG--
extra : convert_revision : d032549e07102bdd50aa09f044fce8de6f0239b5
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builds, runs, and gets very very close to completing the hello world
succesfully but there are some minor quirks to iron out. Who would've known a DELAY SLOT introduces that much complexity?! arrgh!
Anyways, a lot of this stuff had to do with my project at MIPS and me needing to know how I was going to get this working for the MIPS
ISA. So I figured I would try to touch it up and throw it in here (I hate to introduce non-completely working components... )
src/arch/alpha/isa/mem.isa:
spacing
src/arch/mips/faults.cc:
src/arch/mips/faults.hh:
Gabe really authored this
src/arch/mips/isa/decoder.isa:
add StoreConditional Flag to instruction
src/arch/mips/isa/formats/basic.isa:
Steven really did this file
src/arch/mips/isa/formats/branch.isa:
fix bug for uncond/cond control
src/arch/mips/isa/formats/mem.isa:
Adjust O3CPU memory access to use new memory model interface.
src/arch/mips/isa/formats/util.isa:
update LoadStoreBase template
src/arch/mips/isa_traits.cc:
update SERIALIZE partially
src/arch/mips/process.cc:
src/arch/mips/process.hh:
no need for this for NOW. ASID/Virtual addressing handles it
src/arch/mips/regfile/misc_regfile.hh:
add in clear() function and comments for future usage of special misc. regs
src/cpu/base_dyn_inst.hh:
add in nextNPC variable and supporting functions.
add isCondDelaySlot function
Update predTaken and mispredicted functions
src/cpu/base_dyn_inst_impl.hh:
init nextNPC
src/cpu/o3/SConscript:
add MIPS files to compile
src/cpu/o3/alpha/thread_context.hh:
no need for my name on this file
src/cpu/o3/bpred_unit_impl.hh:
Update RAS appropriately for MIPS
src/cpu/o3/comm.hh:
add some extra communication variables to aid in handling the
delay slots
src/cpu/o3/commit.hh:
minor name fix for nextNPC functions.
src/cpu/o3/commit_impl.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
Fix necessary variables and functions for squashes with delay slots
src/cpu/o3/cpu.cc:
Update function interface ...
adjust removeInstsNotInROB function to recognize delay slots insts
src/cpu/o3/cpu.hh:
update removeInstsNotInROB
src/cpu/o3/decode.hh:
declare necessary variables for handling delay slot
src/cpu/o3/dyn_inst.hh:
Add in MipsDynInst
src/cpu/o3/fetch.hh:
src/cpu/o3/iew.hh:
src/cpu/o3/rename.hh:
declare necessary variables and adjust functions for handling delay slot
src/cpu/o3/inst_queue.hh:
src/cpu/simple/base.cc:
no need for my name here
src/cpu/o3/isa_specific.hh:
add in MIPS files
src/cpu/o3/scoreboard.hh:
dont include alpha specific isa traits!
src/cpu/o3/thread_context.hh:
no need for my name here, i just rearranged where the file goes
src/cpu/static_inst.hh:
add isCondDelaySlot function
src/cpu/o3/mips/cpu.cc:
src/cpu/o3/mips/cpu.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/mips/dyn_inst.cc:
src/cpu/o3/mips/dyn_inst.hh:
src/cpu/o3/mips/dyn_inst_impl.hh:
src/cpu/o3/mips/impl.hh:
src/cpu/o3/mips/params.hh:
src/cpu/o3/mips/thread_context.cc:
src/cpu/o3/mips/thread_context.hh:
MIPS file for O3CPU...mirrors ALPHA definition
--HG--
extra : convert_revision : 9bb199b4085903e49ffd5a4c8ac44d11460d988c
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suspend context will now take the thread off the activeThread list.
src/arch/mips/isa_traits.cc:
add in copy MiscRegs unimplemented function
--HG--
extra : convert_revision : 3ed5320b3786f84d4bb242e3a32b6f415339c3ba
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stack space instead of all stacks start to space
src/arch/mips/isa_traits.hh:
MaxAddr is defined in config.py now
src/arch/mips/process.cc:
adjust process so SMT threads get their own stack space
src/arch/mips/process.hh:
add stack_start static variable
--HG--
extra : convert_revision : 73fdf3da9831d86536651835d209806c7f0d59da
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src/arch/mips/isa/formats/fp.isa:
Adjust for newmem
src/cpu/cpu_models.py:
Use O3DynInst instead of convoluted way
src/cpu/o3/alpha/impl.hh:
take out O3DynInst typedef here ...
src/cpu/o3/cpu.cc:
open up the SMT functions in the O3CPU
src/cpu/static_inst.hh:
Add O3DynInst
src/cpu/o3/dyn_inst.hh:
Use to get ISA-specific O3DynInst
--HG--
extra : convert_revision : 3713187ead93e336e80889e23a1f1d2f36d664fe
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src/cpu/simple/base.cc:
add syscall emulation page table fault so we can allocate more stack pages
FaultBase::invoke will do this, we don't need to do it here
src/sim/faults.hh:
I have no idea why this #if was there... gone
src/sim/process.cc:
make stack_min actually be the current minimum
--HG--
extra : convert_revision : 9786b39f2747b94654a5d77c74243cd20503add4
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Fix some author stuff and copyright dates
Take out full system code
src/arch/mips/isa/base.isa:
src/arch/mips/isa/bitfields.isa:
copyright info
src/arch/mips/isa/decoder.isa:
src/arch/mips/isa/formats/basic.isa:
src/arch/mips/isa/formats/branch.isa:
src/arch/mips/isa/formats/control.isa:
src/arch/mips/isa/formats/fp.isa:
src/arch/mips/isa/formats/int.isa:
src/arch/mips/isa/formats/mem.isa:
src/arch/mips/isa/formats/noop.isa:
src/arch/mips/isa/formats/tlbop.isa:
src/arch/mips/isa/formats/trap.isa:
src/arch/mips/isa/formats/unimp.isa:
src/arch/mips/isa/formats/unknown.isa:
src/arch/mips/isa/formats/util.isa:
src/arch/mips/isa/includes.isa:
src/arch/mips/isa/main.isa:
src/arch/mips/isa/operands.isa:
src/arch/mips/process.cc:
src/arch/mips/regfile/misc_regfile.hh:
src/arch/mips/stacktrace.hh:
copyright 2006
src/arch/mips/isa_traits.cc:
src/arch/mips/isa_traits.hh:
copyright 2006
take out full system
src/arch/mips/regfile/float_regfile.hh:
src/arch/mips/regfile/regfile.hh:
copyright 2006
use FloatRegVal
src/arch/mips/regfile/int_regfile.hh:
copyright 2006
move HI/LO to types.hh
src/arch/mips/types.hh:
copyright 2006
typedef FloatRegVal
--HG--
extra : convert_revision : 1d0d72cd655a4e28622745a6c6b06349da533a1d
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src/arch/mips/isa/formats/trap.isa:
Take out fix that tried to fix trap
instruction disassembly. It forces bad
compile ..
configs/test/test.py:
add 'cycle' to exit message
--HG--
extra : convert_revision : 568877797fd2806416b4cbb388cc3f7eb2492627
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-noop templates
-trap disassembly
src/arch/mips/isa/decoder.isa:
luxc1 uses doubleword, not single
src/arch/mips/isa/formats/int.isa:
use new nop decode template
src/arch/mips/isa/formats/mem.isa:
Noop templates
src/arch/mips/isa/formats/noop.isa:
redo noop templates
src/arch/mips/isa/formats/trap.isa:
fix for trap disassembly
--HG--
extra : convert_revision : 56f13e88abdcbd03ab828cff5d775c993157ae96
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into zizzer.eecs.umich.edu:/.automount/zooks/y/ksewell/research/m5-sim/newmem-release
--HG--
extra : convert_revision : 18a381fa230f2ef6d027359ffd619e3ae75cd446
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bcak to main LiveProcess, then automatically select
ISA based on object file type. Now simulation scripts
no longer need to care about the ISA, as they can just
call LiveProcess().
configs/test/test.py:
Script no longer cares about ISA.
src/arch/alpha/process.cc:
src/arch/alpha/process.hh:
src/arch/mips/process.cc:
src/arch/mips/process.hh:
src/arch/sparc/process.cc:
src/arch/sparc/process.hh:
src/sim/process.cc:
src/sim/process.hh:
Move create() from arch-specific files back to
main LiveProcess, then automatically select ISA
based on object file type.
--HG--
extra : convert_revision : ef33ffdc79623b77000f5d68edd2026760b76ab6
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src/arch/mips/SConscript:
remove full-system
src/arch/mips/stacktrace.hh:
alpha to mips
--HG--
extra : convert_revision : 5aa7ba6a4af4884e911708608dfc5a552f70654d
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src/arch/mips/isa/decoder.isa:
div,divu,ext,seb,seh, fp conditonal moves, fp indexed memory...
src/arch/mips/isa/formats/mem.isa:
MemoryNoDisp class .. use sext<> function instead of doing it manually
src/arch/mips/regfile/float_regfile.hh:
use bits function
--HG--
extra : convert_revision : cbbda9499185b91bdb2a6198fe1b961be04f9265
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src/arch/mips/isa/formats/mt.isa:
change copyright to 2006
src/cpu/simple/base.cc:
Only DPRINT NNPC if we are not using ALPHA
src/cpu/static_inst.hh:
Take Out MIPS Specific functions ...
--HG--
extra : convert_revision : 7a69e80cd1564fa3b778b9dade0e9fe3cef94e64
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--HG--
extra : convert_revision : 10c894365fa93eeb44528c29358ad73342f86902
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use ThreadContext rename
src/arch/mips/isa/formats/branch.isa:
src/arch/mips/isa/formats/fp.isa:
src/arch/mips/isa/includes.isa:
Use ThreadContext
src/sim/syscall_emul.cc:
fcntl64 function using TC
src/sim/syscall_emul.hh:
Add fcntl64func
--HG--
extra : convert_revision : b5e2348530473704388b1c5a2b59bf78360260a9
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