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path: root/src/arch/mips
AgeCommit message (Expand)Author
2015-05-05mem, cpu: Add a separate flag for strictly ordered memoryAndreas Sandberg
2015-02-16arch: Make readMiscRegNoEffect const throughoutAndreas Hansson
2015-02-11sim: Move the BaseTLB to src/arch/generic/Andreas Sandberg
2014-12-05misc: Generalize GDB single stepping.Gabe Black
2014-12-05misc: Make the GDB register cache accessible in various sized chunks.Gabe Black
2014-12-02cpu: Always mask the snoop address when performing lock checkAndreas Hansson
2014-11-23mem: Page Table map api modificationAlexandru Dutu
2014-11-23kvm, x86: Adding support for SE mode executionAlexandru Dutu
2014-10-22sim: revert 6709bbcf564dNilay Vaish
2014-10-20sim: implement getdents/getdents64 in user modeMichael Adler
2014-10-16arch: Use shared_ptr for all FaultsAndreas Hansson
2014-09-27arch: Use const StaticInstPtr references where possibleAndreas Hansson
2014-09-20alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivateMitch Hayenga
2014-09-03arch: Cleanup unused ISA traits constantsAndreas Hansson
2014-08-28mem: adding architectural page table support for SE modeAlexandru
2014-08-26mips: Fix RLIMIT_RSS namingMitch Hayenga
2014-08-13mips: Remove unused private members to fix compile-time warningAndreas Sandberg
2014-06-30power: Add basic DVFS support for gem5Stephan Diestelhorst
2014-05-31style: eliminate equality tests with true and falseSteve Reinhardt
2014-05-12syscall emulation: clean up & comment SyscallReturnSteve Reinhardt
2014-05-09arch: teach ISA parser how to split code across filesCurtis Dunham
2014-05-09arch, arm: Preserve TLB bootUncacheability when switching CPUsGeoffrey Blake
2014-05-09arch: remove inline specifiers on all inst constrs, all ISAsCurtis Dunham
2014-03-01cpu: Enable fast-forwarding for MIPS InOrderCPU and O3CPUChristopher Torng
2014-01-24arch: Make all register index flattening constAndreas Hansson
2014-01-24arch, cpu: Add support for flattening misc register indexes.Ali Saidi
2014-01-24cpu: Add CPU support for generatig wake up events when LLSC adresses are snoo...Ali Saidi
2013-12-29mips: Floating point convert bug fixChristopher Torng
2013-10-15cpu: add a condition-code register classYasuko Eckert
2013-10-15cpu: rename *_DepTag constants to *_Reg_BaseSteve Reinhardt
2013-10-15isa: clean up register constantsSteve Reinhardt
2013-09-30arch: Add support for m5ops using mmapped IPRsAndreas Sandberg
2013-06-27sim: Add the notion of clock domains to all ClockedObjectsAkash Bagdia
2013-06-03arch: Create a method to finalize physical addressesAndreas Sandberg
2013-02-19scons: Add warning for missing declarationsAndreas Hansson
2013-02-19scons: Add warning for overloaded virtual functionsAndreas Hansson
2013-02-19scons: Add warning for overloaded virtual functionsAndreas Hansson
2013-01-22x86, cpu: corrects 270c9a75e91f, take over decoder on cpu switchNilay Vaish
2013-01-12x86: Changes to decoder, corrects 9376Nilay Vaish
2013-01-07arch: Move the ISA object to a separate sectionAndreas Sandberg
2013-01-07arch: Make the ISA class inherit from SimObjectAndreas Sandberg
2013-01-07o3: Fix issue with LLSC ordering and speculationAli Saidi
2013-01-04Decoder: Remove the thread context get/set from the decoder.Gabe Black
2012-11-02sim: Include object header files in SWIG interfacesAndreas Sandberg
2012-11-02mips: Remove unused Python fileAndreas Sandberg
2012-11-02ISA: generic Linux thread info supportDam Sunwoo
2012-10-15Checkpoint: Make system serialize call childrenAndreas Hansson
2012-08-28Clock: Add a Cycles wrapper class and use where applicableAndreas Hansson
2012-08-15sysemul: bump all linux versions of for syscal emulation to 3.0.Ali Saidi
2012-08-06syscall emulation: Enabled getrlimit and getrusage for x86.Marc Orr