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AgeCommit message (Expand)Author
2009-07-08Registers: Add a registers.hh file as an ISA switched header.Gabe Black
2009-07-08Registers: Collapse ARM and MIPS regfile directories.Gabe Black
2009-07-08Registers: Eliminate the ISA defined RegFile class.Gabe Black
2009-07-08Registers: Move the PCs out of the ISAs and into the CPUs.Gabe Black
2009-07-08MIPS: Get rid of an orphaned MIPS .cc file.Gabe Black
2009-07-08MIPS: Phase out MIPS's int_regfile.hh.Gabe Black
2009-07-08Registers: Eliminate the ISA defined integer register file.Gabe Black
2009-07-08Registers: Eliminate the ISA defined floating point register file.Gabe Black
2009-07-08Registers: Get rid of the float register width parameter.Gabe Black
2009-07-08Registers: Add an ISA object which replaces the MiscRegFile.Gabe Black
2009-05-26types: add a type for thread IDs and try to use it everywhereNathan Binkert
2009-05-17includes: sort includes againNathan Binkert
2009-05-17types: Move stuff for global types into src/base/types.hhNathan Binkert
2009-05-13inorder-mips: Remove eaComp & memAcc; use 'visible' eaCompKorey Sewell
2009-05-13arch-mips: add regWidth constant to float regfileKorey Sewell
2009-05-12inorder-alpha-port: initial inorder support of ALPHAKorey Sewell
2009-04-21syscall: Resolve conflicts between m5threads and Gabe's recent SE changes.Steve Reinhardt
2009-04-19Memory: Rename LOCKED for load locked store conditional to LLSC.Gabe Black
2009-04-18mips-tlb-fix: check for alignment faults.\nMIPS was never updated to use TLBS...Korey Sewell
2009-04-18mips-syscall: mark with correct flag. \nMIPS was using wrong serialization fl...Korey Sewell
2009-04-18o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode ...Korey Sewell
2009-04-18mips-shadowsets: fix calcuations. \n Remove Shadowsets from Int & Arch. Reg ...Korey Sewell
2009-04-08tlb: More fixing of unified TLBNathan Binkert
2009-04-08tlb: Don't separate the TLB classes into an instruction TLB and a data TLBGabe Black
2009-03-05stats: Fix all stats usages to deal with template fixesNathan Binkert
2009-03-05Get rid of 'using namespace' declarations in headers.Steve Reinhardt
2009-02-28Fix Num_Syscall_Descs check bug in non-x86 ISAs.Steve Reinhardt
2009-02-27Processes: Make getting and setting system call arguments part of a process o...Gabe Black
2009-02-25ISA: Get rid of the get*RegName functions.Gabe Black
2009-02-25CPU: Implement translateTiming which defers to translateAtomic, and convert t...Gabe Black
2009-02-25ISA: Replace the translate functions in the TLBs with translateAtomic.Gabe Black
2009-02-20Remove unnecessary building of FreeList/RenameMap in InOrder. Clean-up commen...Korey Sewell
2009-02-16sycalls: implement mremap() and add DATA flag for getrlimit(). mremap has bee...Lisa Hsu
2009-02-10syscall: Expose ioctl for MIPSKorey Sewell
2009-01-13SCons: centralize the Dir() workaround for newer versions of scons.Nathan Binkert
2008-11-15syscalls: fix latent brk/obreak bug.Steve Reinhardt
2008-11-14Fix a bunch of bugs I introduced when I changed the flags stuff for packets.Nathan Binkert
2008-11-10mem: update stuff for changes to Packet and RequestNathan Binkert
2008-11-04get rid of all instances of readTid() and getThreadNum(). Unify and eliminateLisa Hsu
2008-11-02Add in Context IDs to the simulator. From now on, cpuId is almost never used,Lisa Hsu
2008-11-02make BaseCPU the provider of _cpuId, and cpuId() instead of being scatteredLisa Hsu
2008-10-21style: Use the correct m5 style for things relating to interrupts.Nathan Binkert
2008-10-12Get rid of old RegContext code.Gabe Black
2008-10-12CPU: Create a microcode ROM object in the CPU which is defined by the ISA.Gabe Black
2008-10-12Turn Interrupts objects into SimObjects. Also, move local APIC state into x86...Gabe Black
2008-10-12CPU: Eliminate the get_vec function.Gabe Black
2008-10-10TLB: Make all tlbs derive from a common base class in both python and C++.Gabe Black
2008-10-09SimObjects: Clean up handling of C++ namespaces.Nathan Binkert
2008-10-09eventq: convert all usage of events to use the new API.Nathan Binkert
2008-10-09O3: Generaize the O3 dynamic instruction class so it isn't split out by ISA.Gabe Black
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