| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2009-07-10 | ISAs: Get rid of the IControl operand type. | Gabe Black | |
| A separate operand type is not necessary to use two bitfields to generate the index. | |||
| 2009-07-09 | MIPS: Fold the MiscRegFile all the way into the ISA object. | Gabe Black | |
| 2009-07-08 | Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions. | Gabe Black | |
| 2009-07-08 | Registers: Add a registers.hh file as an ISA switched header. | Gabe Black | |
| This file is for register indices, Num* constants, and register types. copyRegs and copyMiscRegs were moved to utility.hh and utility.cc. --HG-- rename : src/arch/alpha/regfile.hh => src/arch/alpha/registers.hh rename : src/arch/arm/regfile.hh => src/arch/arm/registers.hh rename : src/arch/mips/regfile.hh => src/arch/mips/registers.hh rename : src/arch/sparc/regfile.hh => src/arch/sparc/registers.hh rename : src/arch/x86/regfile.hh => src/arch/x86/registers.hh | |||
| 2009-07-08 | Registers: Collapse ARM and MIPS regfile directories. | Gabe Black | |
| --HG-- rename : src/arch/arm/regfile/misc_regfile.hh => src/arch/arm/misc_regfile.hh rename : src/arch/arm/regfile/regfile.cc => src/arch/arm/regfile.cc rename : src/arch/mips/regfile/misc_regfile.cc => src/arch/mips/misc_regfile.cc rename : src/arch/mips/regfile/misc_regfile.hh => src/arch/mips/misc_regfile.hh | |||
| 2009-07-08 | Registers: Eliminate the ISA defined RegFile class. | Gabe Black | |
| 2009-07-08 | Registers: Move the PCs out of the ISAs and into the CPUs. | Gabe Black | |
| 2009-07-08 | MIPS: Get rid of an orphaned MIPS .cc file. | Gabe Black | |
| 2009-07-08 | MIPS: Phase out MIPS's int_regfile.hh. | Gabe Black | |
| 2009-07-08 | Registers: Eliminate the ISA defined integer register file. | Gabe Black | |
| 2009-07-08 | Registers: Eliminate the ISA defined floating point register file. | Gabe Black | |
| 2009-07-08 | Registers: Get rid of the float register width parameter. | Gabe Black | |
| 2009-07-08 | Registers: Add an ISA object which replaces the MiscRegFile. | Gabe Black | |
| This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU. | |||
| 2009-05-26 | types: add a type for thread IDs and try to use it everywhere | Nathan Binkert | |
| 2009-05-17 | includes: sort includes again | Nathan Binkert | |
| 2009-05-17 | types: Move stuff for global types into src/base/types.hh | Nathan Binkert | |
| --HG-- rename : src/sim/host.hh => src/base/types.hh | |||
| 2009-05-13 | inorder-mips: Remove eaComp & memAcc; use 'visible' eaComp | Korey Sewell | |
| Inorder expects eaComp to be visible through StaticInst object. This mirrors a similar change to ALPHA... Needs to be done for SPARC and whatever other ISAs want to use InOrderCPU | |||
| 2009-05-13 | arch-mips: add regWidth constant to float regfile | Korey Sewell | |
| 2009-05-12 | inorder-alpha-port: initial inorder support of ALPHA | Korey Sewell | |
| Edit AlphaISA to support the inorder model. Mostly alternate constructor functions and also a few skeleton multithreaded support functions * * * Remove namespace from header file. Causes compiler issues that are hard to find * * * Separate the TLB from the CPU and allow it to live in the TLBUnit resource. Give CPU accessor functions for access and also bind at construction time * * * Expose memory access size and flags through instruction object (temporarily memAccSize and memFlags to get TLB stuff working.) | |||
| 2009-04-21 | syscall: Resolve conflicts between m5threads and Gabe's recent SE changes. | Steve Reinhardt | |
| 2009-04-19 | Memory: Rename LOCKED for load locked store conditional to LLSC. | Gabe Black | |
| 2009-04-18 | mips-tlb-fix: check for alignment faults.\nMIPS was never updated to use ↵ | Korey Sewell | |
| TLBS correcty in SE mode. The error was forwarding translations directly to pageTable. The TLB should check for alignment faults at bare minimum here but in the long run we should be using TLBs in SE mode for MIPS. | |||
| 2009-04-18 | mips-syscall: mark with correct flag. \nMIPS was using wrong serialization ↵ | Korey Sewell | |
| flag on syscall instructions allowing O3 to handle SE mode syscalls incorrectly and speculate on instructions after a syscall | |||
| 2009-04-18 | o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode ↵ | Korey Sewell | |
| stage was not setting the predicted PC correctly or passing that information back to fetch correctly | |||
| 2009-04-18 | mips-shadowsets: fix calcuations. \n Remove Shadowsets from Int & Arch. Reg ↵ | Korey Sewell | |
| Calculations | |||
| 2009-04-08 | tlb: More fixing of unified TLB | Nathan Binkert | |
| 2009-04-08 | tlb: Don't separate the TLB classes into an instruction TLB and a data TLB | Gabe Black | |
| 2009-03-05 | stats: Fix all stats usages to deal with template fixes | Nathan Binkert | |
| 2009-03-05 | Get rid of 'using namespace' declarations in headers. | Steve Reinhardt | |
| 2009-02-28 | Fix Num_Syscall_Descs check bug in non-x86 ISAs. | Steve Reinhardt | |
| (See cset d35d2b28df38 for x86 fix.) | |||
| 2009-02-27 | Processes: Make getting and setting system call arguments part of a process ↵ | Gabe Black | |
| object. | |||
| 2009-02-25 | ISA: Get rid of the get*RegName functions. | Gabe Black | |
| 2009-02-25 | CPU: Implement translateTiming which defers to translateAtomic, and convert ↵ | Gabe Black | |
| the timing simple CPU to use it. | |||
| 2009-02-25 | ISA: Replace the translate functions in the TLBs with translateAtomic. | Gabe Black | |
| 2009-02-20 | Remove unnecessary building of FreeList/RenameMap in InOrder. Clean-up ↵ | Korey Sewell | |
| comments and O3 extensions InOrder Thread Context | |||
| 2009-02-16 | sycalls: implement mremap() and add DATA flag for getrlimit(). mremap has ↵ | Lisa Hsu | |
| been tested on Alpha, compiles for the rest but not tested. I don't see why it wouldn't work though. | |||
| 2009-02-10 | syscall: Expose ioctl for MIPS | Korey Sewell | |
| 2009-01-13 | SCons: centralize the Dir() workaround for newer versions of scons. | Nathan Binkert | |
| Scons bug id: 2006 M5 Bug id: 308 | |||
| 2008-11-15 | syscalls: fix latent brk/obreak bug. | Steve Reinhardt | |
| Bogus calls to ChunkGenerator with negative size were triggering a new assertion that was added there. Also did a little renaming and cleanup in the process. | |||
| 2008-11-14 | Fix a bunch of bugs I introduced when I changed the flags stuff for packets. | Nathan Binkert | |
| I did some of the flags and assertions wrong. Thanks to Brad Beckmann for pointing this out. I should have run the opt regressions instead of the fast. I also screwed up some of the logical functions in the Flags class. | |||
| 2008-11-10 | mem: update stuff for changes to Packet and Request | Nathan Binkert | |
| 2008-11-04 | get rid of all instances of readTid() and getThreadNum(). Unify and eliminate | Lisa Hsu | |
| redundancies with threadId() as their replacement. | |||
| 2008-11-02 | Add in Context IDs to the simulator. From now on, cpuId is almost never used, | Lisa Hsu | |
| the primary identifier for a hardware context should be contextId(). The concept of threads within a CPU remains, in the form of threadId() because sometimes you need to know which context within a cpu to manipulate. | |||
| 2008-11-02 | make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered | Lisa Hsu | |
| across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. | |||
| 2008-10-21 | style: Use the correct m5 style for things relating to interrupts. | Nathan Binkert | |
| 2008-10-12 | Get rid of old RegContext code. | Gabe Black | |
| 2008-10-12 | CPU: Create a microcode ROM object in the CPU which is defined by the ISA. | Gabe Black | |
| 2008-10-12 | Turn Interrupts objects into SimObjects. Also, move local APIC state into ↵ | Gabe Black | |
| x86's Interrupts object. | |||
| 2008-10-12 | CPU: Eliminate the get_vec function. | Gabe Black | |
| 2008-10-10 | TLB: Make all tlbs derive from a common base class in both python and C++. | Gabe Black | |
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