index
:
gem5
hitsb
invisispec-1.0
invisispec-with-dift
is-ift
is-ift-cachehit
is-rebase
is-rebase-new
is-rebase-new2
is-rebase-new3-rdtscp
is-rebase04-linux3.2
is-rebase05
is-rebase06-RequestPtr
is-rebase07-GCC8
is-rebase08-QoSmem
is-rebase09-linuxarm-3.7.0
is-rebase10-DynInstPtr
is-rebase11-LSQUnit
is-rebase12
simple-object-demo
gem5
summary
refs
log
tree
commit
diff
log msg
author
committer
range
path:
root
/
src
/
arch
/
mips
Age
Commit message (
Expand
)
Author
2009-07-08
Get rid of the unused get(Data|Inst)Asid and (inst|data)Asid functions.
Gabe Black
2009-07-08
Registers: Add a registers.hh file as an ISA switched header.
Gabe Black
2009-07-08
Registers: Collapse ARM and MIPS regfile directories.
Gabe Black
2009-07-08
Registers: Eliminate the ISA defined RegFile class.
Gabe Black
2009-07-08
Registers: Move the PCs out of the ISAs and into the CPUs.
Gabe Black
2009-07-08
MIPS: Get rid of an orphaned MIPS .cc file.
Gabe Black
2009-07-08
MIPS: Phase out MIPS's int_regfile.hh.
Gabe Black
2009-07-08
Registers: Eliminate the ISA defined integer register file.
Gabe Black
2009-07-08
Registers: Eliminate the ISA defined floating point register file.
Gabe Black
2009-07-08
Registers: Get rid of the float register width parameter.
Gabe Black
2009-07-08
Registers: Add an ISA object which replaces the MiscRegFile.
Gabe Black
2009-05-26
types: add a type for thread IDs and try to use it everywhere
Nathan Binkert
2009-05-17
includes: sort includes again
Nathan Binkert
2009-05-17
types: Move stuff for global types into src/base/types.hh
Nathan Binkert
2009-05-13
inorder-mips: Remove eaComp & memAcc; use 'visible' eaComp
Korey Sewell
2009-05-13
arch-mips: add regWidth constant to float regfile
Korey Sewell
2009-05-12
inorder-alpha-port: initial inorder support of ALPHA
Korey Sewell
2009-04-21
syscall: Resolve conflicts between m5threads and Gabe's recent SE changes.
Steve Reinhardt
2009-04-19
Memory: Rename LOCKED for load locked store conditional to LLSC.
Gabe Black
2009-04-18
mips-tlb-fix: check for alignment faults.\nMIPS was never updated to use TLBS...
Korey Sewell
2009-04-18
mips-syscall: mark with correct flag. \nMIPS was using wrong serialization fl...
Korey Sewell
2009-04-18
o3-delay-slot-bpred: fix decode stage handling of uncdtl. branches.\n decode ...
Korey Sewell
2009-04-18
mips-shadowsets: fix calcuations. \n Remove Shadowsets from Int & Arch. Reg ...
Korey Sewell
2009-04-08
tlb: More fixing of unified TLB
Nathan Binkert
2009-04-08
tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
Gabe Black
2009-03-05
stats: Fix all stats usages to deal with template fixes
Nathan Binkert
2009-03-05
Get rid of 'using namespace' declarations in headers.
Steve Reinhardt
2009-02-28
Fix Num_Syscall_Descs check bug in non-x86 ISAs.
Steve Reinhardt
2009-02-27
Processes: Make getting and setting system call arguments part of a process o...
Gabe Black
2009-02-25
ISA: Get rid of the get*RegName functions.
Gabe Black
2009-02-25
CPU: Implement translateTiming which defers to translateAtomic, and convert t...
Gabe Black
2009-02-25
ISA: Replace the translate functions in the TLBs with translateAtomic.
Gabe Black
2009-02-20
Remove unnecessary building of FreeList/RenameMap in InOrder. Clean-up commen...
Korey Sewell
2009-02-16
sycalls: implement mremap() and add DATA flag for getrlimit(). mremap has bee...
Lisa Hsu
2009-02-10
syscall: Expose ioctl for MIPS
Korey Sewell
2009-01-13
SCons: centralize the Dir() workaround for newer versions of scons.
Nathan Binkert
2008-11-15
syscalls: fix latent brk/obreak bug.
Steve Reinhardt
2008-11-14
Fix a bunch of bugs I introduced when I changed the flags stuff for packets.
Nathan Binkert
2008-11-10
mem: update stuff for changes to Packet and Request
Nathan Binkert
2008-11-04
get rid of all instances of readTid() and getThreadNum(). Unify and eliminate
Lisa Hsu
2008-11-02
Add in Context IDs to the simulator. From now on, cpuId is almost never used,
Lisa Hsu
2008-11-02
make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered
Lisa Hsu
2008-10-21
style: Use the correct m5 style for things relating to interrupts.
Nathan Binkert
2008-10-12
Get rid of old RegContext code.
Gabe Black
2008-10-12
CPU: Create a microcode ROM object in the CPU which is defined by the ISA.
Gabe Black
2008-10-12
Turn Interrupts objects into SimObjects. Also, move local APIC state into x86...
Gabe Black
2008-10-12
CPU: Eliminate the get_vec function.
Gabe Black
2008-10-10
TLB: Make all tlbs derive from a common base class in both python and C++.
Gabe Black
2008-10-09
SimObjects: Clean up handling of C++ namespaces.
Nathan Binkert
2008-10-09
eventq: convert all usage of events to use the new API.
Nathan Binkert
[prev]
[next]