gem5 - gem5

Age	Commit message (Expand)	Author
2019-02-01	cpu, arch: Replace the CCReg type with RegVal.	Gabe Black
2019-01-31	null: Get rid of some register type definitions.	Gabe Black
2019-01-31	arch: cpu: Rename FloatRegBits to FloatReg.	Gabe Black
2019-01-30	arch,cpu: Add vector predicate registers	Giacomo Gabrielli
2019-01-24	base: arch: Get rid of the now unused FloatRegVal type.	Gabe Black
2019-01-16	arch: Make the ISA register types aliases for the global types.	Gabe Black
2018-11-05	null: Claim to use 64 bit floating point registers.	Gabe Black
2018-10-18	null: Stop specifying an endianness in isa_traits.hh.	Gabe Black
2017-10-17	scons: Stop generating inc.d in the isa parser.	Gabe Black
2017-10-13	mem: Signal the local monitor when clearing the global monitor	Nikos Nikoleris
2017-07-05	cpu: Added interface for vector reg file	Rekai Gonzalez-Alberquilla
2017-07-05	arch, cpu: Architectural Register structural indexing	Nathanael Premillieu
2015-09-30	cpu,isa,mem: Add per-thread wakeup logic	Mitch Hayenga
2015-07-28	revert 5af8f40d8f2c	Nilay Vaish
2015-07-26	cpu: implements vector registers	Nilay Vaish
2014-09-03	arch: Cleanup unused ISA traits constants	Andreas Hansson
2014-05-09	arch: teach ISA parser how to split code across files	Curtis Dunham
2014-03-07	mem: Wakeup sleeping CPUs without caches on LLSC	Ali Saidi
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
2013-09-04	arch: Resurrect the NOISA build target and rename it NULL	Andreas Hansson