gem5 - gem5

Age	Commit message (Collapse)	Author
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
	The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers. This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU.
2012-06-05	ISA: Back-out NoopMachInst as a StaticInstPtr change.	Ali Saidi

2012-06-04	ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.	Gabe Black
	This eliminates a use of the ExtMachInst type outside of the ISAs.
2012-05-25	ISA: Make the decode function part of the ISA's decoder.	Gabe Black

2011-11-13	Power: Add a stubbed out stacktrace.cc	Gabe Black

2011-10-30	SE/FS: Remove the last references to FULL_SYSTEM from POWER.	Gabe Black

2011-10-16	Power: Add a stub implementation for vtophys in SE and FS.	Gabe Black

2011-10-09	SE/FS: Build the Interrupt objects in SE mode.	Gabe Black

2011-06-02	scons: rename TraceFlags to DebugFlags	Nathan Binkert

2010-07-22	Power: Provide a utility function to copy registers from one thread context	Timothy M. Jones
	to another in the Power ISA.
2009-10-27	POWER: Add support for the Power ISA	Timothy M. Jones
	This adds support for the 32-bit, big endian Power ISA. This supports both integer and floating point instructions based on the Power ISA Book I v2.06.