gem5 - gem5

Age	Commit message (Expand)	Author
2017-12-04	misc: Rename misc.(hh\|cc) to logging.(hh\|cc)	Gabe Black
2017-07-05	cpu: Added interface for vector reg file	Rekai Gonzalez-Alberquilla
2017-07-05	cpu: Simplify the rename interface and use RegId	Rekai Gonzalez-Alberquilla
2015-07-28	revert 5af8f40d8f2c	Nilay Vaish
2015-07-26	cpu: implements vector registers	Nilay Vaish
2015-02-16	arch: Make readMiscRegNoEffect const throughout	Andreas Hansson
2014-01-24	arch: Make all register index flattening const	Andreas Hansson
2014-01-24	arch, cpu: Add support for flattening misc register indexes.	Ali Saidi
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
2013-02-19	scons: Add warning for overloaded virtual functions	Andreas Hansson
2013-01-12	x86: Changes to decoder, corrects 9376	Nilay Vaish
2013-01-07	arch: Move the ISA object to a separate section	Andreas Sandberg
2013-01-07	arch: Make the ISA class inherit from SimObject	Andreas Sandberg
2011-01-03	Make commenting on close namespace brackets consistent.	Steve Reinhardt
2009-10-27	POWER: Add support for the Power ISA	Timothy M. Jones