gem5 - gem5

Age	Commit message (Collapse)	Author
2015-07-28	revert 5af8f40d8f2c	Nilay Vaish

2015-07-26	cpu: implements vector registers	Nilay Vaish
	This adds a vector register type. The type is defined as a std::array of a fixed number of uint64_ts. The isa_parser.py has been modified to parse vector register operands and generate the required code. Different cpus have vector register files now.
2013-10-15	cpu: add a condition-code register class	Yasuko Eckert
	Add a third register class for condition codes, in parallel with the integer and FP classes. No ISAs use the CC class at this point though.
2013-10-15	cpu: rename _DepTag constants to _Reg_Base	Steve Reinhardt
	Make these names more meaningful. Specifically, made these substitutions: s/FP_Base_DepTag/FP_Reg_Base/g; s/Ctrl_Base_DepTag/Misc_Reg_Base/g; s/Max_DepTag/Max_Reg_Index/g;
2012-06-08	Power: Fix MaxMiscDestRegs which was set to zero	Andreas Hansson
	This patch fixes a failing compilation caused by MaxMiscDestRegs being zero. According to gcc 4.6, the result is a comparison that is always false due to limited range of data type.
2012-06-05	O3: Clean up the O3 structures and try to pack them a bit better.	Ali Saidi
	DynInst is extremely large the hope is that this re-organization will put the most used members close to each other.
2012-04-23	ISA: Put parser generated files in a "generated" directory.	Gabe Black
	This is to avoid collision with non-generated files.
2011-01-03	Make commenting on close namespace brackets consistent.	Steve Reinhardt
	Ran all the source files through 'perl -pi' with this script: s\|\s(};?\s)?/\\s(end\s)?namespace\s(\S+)\s\/(\s})?\|} // namespace $3\|; s\|\s};?\s//\s(end\s)?namespace\s(\S+)\s\|} // namespace $2\n\|; s\|\s};?\s//\s(\S+)\snamespace\s\|} // namespace $1\n\|; Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript.
2010-08-25	ARM: Fixed register flattening logic (FP_Base_DepTag was set too low)	Min Kyu Jeong
	When decoding a srs instruction, invalid mode encoding returns invalid instruction. This can happen when garbage instructions are fetched from mispredicted path
2009-10-27	POWER: Add support for the Power ISA	Timothy M. Jones
	This adds support for the 32-bit, big endian Power ISA. This supports both integer and floating point instructions based on the Power ISA Book I v2.06.