gem5 - gem5

Age	Commit message (Collapse)	Author
2015-05-05	mem, cpu: Add a separate flag for strictly ordered memory	Andreas Sandberg
	The Request::UNCACHEABLE flag currently has two different functions. The first, and obvious, function is to prevent the memory system from caching data in the request. The second function is to prevent reordering and speculation in CPU models. This changeset gives the order/speculation requirement a separate flag (Request::STRICT_ORDER). This flag prevents CPU models from doing the following optimizations: * Speculation: CPU models are not allowed to issue speculative loads. * Write combining: CPU models and caches are not allowed to merge writes to the same cache line. Note: The memory system may still reorder accesses unless the UNCACHEABLE flag is set. It is therefore expected that the STRICT_ORDER flag is combined with the UNCACHEABLE flag to prevent this behavior.
2014-10-16	arch: Use shared_ptr for all Faults	Andreas Hansson
	This patch takes quite a large step in transitioning from the ad-hoc RefCountingPtr to the c++11 shared_ptr by adopting its use for all Faults. There are no changes in behaviour, and the code modifications are mostly just replacing "new" with "make_shared".
2014-05-31	style: eliminate equality tests with true and false	Steve Reinhardt
	Using '== true' in a boolean expression is totally redundant, and using '== false' is pretty verbose (and arguably less readable in most cases) compared to '!'. It's somewhat of a pet peeve, perhaps, but I had some time waiting for some tests to run and decided to clean these up. Unfortunately, SLICC appears not to have the '!' operator, so I had to leave the '== false' tests in the SLICC code.
2013-06-03	arch: Create a method to finalize physical addresses	Andreas Sandberg
	in the TLB Some architectures (currently only x86) require some fixing-up of physical addresses after a normal address translation. This is usually to remap devices such as the APIC, but could be used for other memory mapped devices as well. When running the CPU in a using hardware virtualization, we still need to do these address fix-ups before inserting the request into the memory system. This patch moves this patch allows that code to be used by such CPUs without doing full address translations.
2012-03-09	CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU	Geoffrey Blake
	Making the CheckerCPU a runtime time option requires the code to be compatible with ISAs other than ARM. This patch adds the appropriate function stubs to allow compilation.
2012-01-29	Implement Ali's review feedback.	Gabe Black
	Try to decrease indentation, and remove some redundant FullSystem checks.
2012-01-07	Merge with main repository.	Gabe Black

2011-10-31	GCC: Get everything working with gcc 4.6.1.	Gabe Black
	And by "everything" I mean all the quick regressions.
2011-10-30	SE/FS: Remove the last references to FULL_SYSTEM from POWER.	Gabe Black

2011-04-15	trace: reimplement the DTRACE function so it doesn't use a vector	Nathan Binkert
	At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
2010-09-10	style: fix sorting of includes and whitespace in some files	Nathan Binkert

2010-06-15	stats: only consider a formula initialized if there is a formula	Nathan Binkert

2010-02-12	Power ISA: Add an alignment fault to Power ISA and check alignment in TLB.	Timothy M. Jones

2009-10-27	POWER: Add support for the Power ISA	Timothy M. Jones
	This adds support for the 32-bit, big endian Power ISA. This supports both integer and floating point instructions based on the Power ISA Book I v2.06.