| Age | Commit message (Expand) | Author |
|---|
| 2019-11-18 | arch: Get rid of the (Big|Little)EndianGuest namespaces. | Gabe Black |
| 2019-11-18 | arch: Make and use endian specific versions of the mem helpers. | Gabe Black |
| 2019-11-07 | power: Replace gtoh and htog with betoh and htobe. | Gabe Black |
| 2019-11-02 | arch,cpu: Move endianness conversion of inst bytes into the ISA. | Gabe Black |
| 2019-10-30 | arch,sim: Make copyStringArray take an explicit endianness. | Gabe Black |
| 2019-10-30 | arch: Make endianness a property of the OS class syscalls can consume. | Gabe Black |
| 2019-10-19 | arch: Make a base class for Interrupts. | Gabe Black |
| 2019-10-16 | arch,base,sim: Move Process loader hooks into the Process class. | Gabe Black |
| 2019-10-12 | arch,base: Separate the idea of a memory image and object file. | Gabe Black |
| 2019-10-10 | arch,base: Stop loading the interpreter in ElfObject. | Gabe Black |
| 2019-10-10 | arch, base: Stop assuming object files have three segments. | Gabe Black |
| 2019-10-09 | base: Rename Section to Segment, and some of its members. | Gabe Black |
| 2019-05-30 | arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy. | Gabe Black |
| 2019-05-29 | sim-se: add a release parameter to Process.py | Ciro Santilli |
| 2019-05-29 | arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods. | Gabe Black |
| 2019-05-21 | sim-se: change syscall function signature | Brandon Potter |
| 2019-05-20 | power: Add an object file loader for linux. | Gabe Black |
| 2019-04-30 | arch: Stop using TheISA within the ISAs. | Gabe Black |
| 2019-04-28 | arch, sim: Simplify the AuxVector type. | Gabe Black |
| 2019-03-25 | arch-power: Rename program counter registers | Sandipan Das |
| 2019-03-25 | arch-power: Simplify doubleword operand types | Sandipan Das |
| 2019-02-12 | python: Don't assume SimObjects live in the global namespace | Andreas Sandberg |
| 2019-02-01 | cpu, arch: Replace the CCReg type with RegVal. | Gabe Black |
| 2019-01-31 | power: Get rid of some ISA specific register types. | Gabe Black |
| 2019-01-31 | arch: cpu: Rename *FloatRegBits* to *FloatReg*. | Gabe Black |
| 2019-01-30 | arch,cpu: Add vector predicate registers | Giacomo Gabrielli |
| 2019-01-24 | base: arch: Get rid of the now unused FloatRegVal type. | Gabe Black |
| 2019-01-22 | arch: cpu: Stop passing around misc registers by reference. | Gabe Black |
| 2019-01-22 | sim-se: add syscalls related to polling | Brandon Potter |
| 2019-01-16 | arch: Make the ISA register types aliases for the global types. | Gabe Black |
| 2018-10-17 | arch: Get rid of the unused type AnyReg. | Gabe Black |
| 2018-09-19 | syscall_emul: expand AuxVector class | Brandon Potter |
| 2018-06-11 | misc: Using smart pointers for memory Requests | Giacomo Travaglini |
| 2018-05-08 | arch-x86, arch-power: fix calls to bits and insertBits | Matt Sinclair |
| 2018-03-26 | arch: Fix all override related warnings. | Gabe Black |
| 2018-03-26 | arch: Add a virtual asBytes function to the StaticInst class. | Gabe Black |
| 2018-01-20 | arch, mem: Make the page table lookup function return a pointer. | Gabe Black |
| 2018-01-20 | sim, arch, base: Refactor the base remote GDB class. | Gabe Black |
| 2018-01-19 | arch, mem, sim: Consolidate and rename the SE mode page table classes. | Gabe Black |
| 2018-01-15 | arch: Fix a fatal_if in most of the arch's process classes. | Gabe Black |
| 2018-01-11 | arm, power: Make the python TLB simobjects inherit from BaseTLB. | Gabe Black |
| 2018-01-11 | arch,mem: Remove the default value for page size. | Gabe Black |
| 2018-01-11 | arch,mem: Move page table construction into the arch classes. | Gabe Black |
| 2018-01-10 | style: change C/C++ source permissions to noexec | BKP |
| 2018-01-10 | alpha,arm,mips,power,riscv,sparc,x86,cpu: Get rid of ISA_HAS_DELAY_SLOT. | Gabe Black |
| 2018-01-09 | cpu, power: Get rid of the remnants of the EA computation insts. | Gabe Black |
| 2017-12-23 | alpha,arm,mips,power,riscv,sparc,x86: Get rid of TheISA::NoopMachInst. | Gabe Black |
| 2017-12-22 | arch,cpu: "virtualize" the TLB interface. | Gabe Black |
| 2017-12-13 | cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst. | Gabe Black |
| 2017-12-04 | misc: Rename misc.(hh|cc) to logging.(hh|cc) | Gabe Black |
