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2020-02-01arch,sim: Merge initCPU into the ISA System classes.Gabe Black
Those classes are already ISA specific, so we can just move initCPU's contents there and take it out of utility.hh, utility.cc, and the base System's initState. Change-Id: I28f0d0b50d83efe5116b0b24d20f8182a02823e7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24905 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-02-01arch,sim: Merge initCPU and startupCPU.Gabe Black
These two functions were called in exactly one place one right after the other, and served similar purposes. This change merges them together, and cleans them up slightly. It also removes checks for FullSystem, since those functions are only called in full system to begin with. Change-Id: I214f7d2d3f88960dccb5895c1241f61cd78716a8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24904 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2020-01-22arch: Get rid of the unused (and mostly undefined) zeroRegisters.Gabe Black
Change-Id: Iadf56e4e742506af7ae4b617d2dc5a56439aa407 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24188 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-12-10sim,arch: Collapse the ISA specific versions of m5Syscall.Gabe Black
The x86 version doesn't do anything x86 specific, and so can be used generically in sim/pseudo_inst.(hh|cc) Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I46c2a7d326bd7a95daa8611888051c180e92e446 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23177 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-12-10arch,cpu,sim: Push syscall number determination up to processes.Gabe Black
The logic that determines which syscall to call was built into the implementation of faults/exceptions or even into the instruction decoder, but that logic can depend on what OS is being used, and sometimes even what version, for example 32bit vs. 64bit. This change pushes that logic up into the Process objects since those already handle a lot of the aspects of emulating the guest OS. Instead, the ISA or fault implementations just notify the rest of the system that a nebulous syscall has happened, and that gets propogated upward until the process does something with it. That's very analogous to how a system call would work on a real machine. When a system call happens, the low level component which detects that should call tc->syscall(&fault), where tc is the relevant thread (or execution) context, and fault is a Fault which can ultimately be set by the system call implementation. The TC implementor (probably a CPU) will then have a chance to do whatever it needs to to handle a system call. Currently only O3 does anything special here. That implementor will end up calling the Process's syscall() method. Once in Process::syscall, the process object will use it's contextual knowledge to determine what system call is being requested. It then calls Process::doSyscall with the right syscall number, where doSyscall centralizes the common mechanism for actually retrieving and calling into the system call implementation. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I937ec1ef0576142c2a182ff33ca508d77ad0e7a1 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23176 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2019-12-10arch: Get rid of the now unused setSyscallArg.Gabe Black
Setting syscall args isn't really something we need to do in gem5, since that will be taken care of by the code actually calling the syscall. We just need to be able to retrieve the value it put there. Jira Issue: https://gem5.atlassian.net/browse/GEM5-187 Change-Id: I0bb6d5d0207a7892414a722b3788cb70ee509582 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/23174 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-11-18arch: Get rid of the (Big|Little)EndianGuest namespaces.Gabe Black
These namespaces were used to set up an environment/context where there was an implicit guest namespace. This is an issue when there may be multiple guest endiannesses which might be different. In cases where we don't know what the guest endianness is, we can't rely on it being an implicit part of our context since that would be ambiguous. In cases where we do know, for instance in ISA specific code, we can just use the endianness specific version that's appropriate for that context. This also (somewhat) removes the assumption that there is a single endianness that applies for a particular ISA. Practically speaking this assumption will probably still stand though, since there would likely be a non-trivial performance penalty to apply a configurable endianness instead of a fixed one the compiler can optomize/remove. Change-Id: I2dff338b58726d724f387388efe32d9233885680 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22374 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-18arch: Make and use endian specific versions of the mem helpers.Gabe Black
Rather than using TheISA to pick an endian conversion function, we can have a version defined for big and little endian and call the right one from the ISA code. Change-Id: I5014504968952e21abff3c5f6cbe58ca24233f33 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22373 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-07power: Replace gtoh and htog with betoh and htobe.Gabe Black
We already know what endianness to use when within power. Change-Id: Id4ced279d21c56855307a5a8da51654101a13786 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22371 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-11-02arch,cpu: Move endianness conversion of inst bytes into the ISA.Gabe Black
It doesn't matter if the bytes are converted before or after they're fed into the decoder. The ISA already knows what endianness to use implicitly, and this frees the CPU which doesn't from having to worry about it. Change-Id: Id6574ee81bbf4f032c1d7b2901a664f2bd014fbc Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22343 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30arch,sim: Make copyStringArray take an explicit endianness.Gabe Black
Change-Id: I5cf4291b19dd2d2bdbbf145ad8e00994fabf5547 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22366 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-30arch: Make endianness a property of the OS class syscalls can consume.Gabe Black
That way the syscall implementations won't have to find the right endianness to use on their own, typically by referring to TheISA. Change-Id: I186b2f419d5dbee72cc9b5abce7356f3143f0c83 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22363 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-10-19arch: Make a base class for Interrupts.Gabe Black
That abstracts the ISA further from the CPU, getting us a small step closer to being able to build in more than one ISA at a time. Change-Id: Ibf7e26a3df411ffe994ac1e11d2a53b656863223 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20831 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-10-16arch,base,sim: Move Process loader hooks into the Process class.Gabe Black
This code was originally in the ObjectFile class, but not all object files will become Processes. All Processes will ultimately come from ObjectFiles though, so it makes more sense to put that class there. Change-Id: Ie73e4cdecbb51ce53d24cf68911a6cfc0685d771 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21468 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-10-12arch,base: Separate the idea of a memory image and object file.Gabe Black
A memory image can be described by an object file, but an object file is more than a memory image. Also, it makes sense to manipulate a memory image to, for instance, change how it's loaded into memory. That takes on larger implications (relocations, the entry point, symbols, etc.) when talking about the whole object file, and also modifies aspects which may not need to change. For instance if an image needs to be loaded into memory at addresses different from what's in the object file, but other things like symbols need to stay unmodified. Change-Id: Ia360405ffb2c1c48e0cc201ac0a0764357996a54 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21466 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-10-10arch,base: Stop loading the interpreter in ElfObject.Gabe Black
The interpreter is a separate object file, and while it's convenient to hide loading it in the code which loads the main object file, it breaks the conceptual abstraction since you only asked it to load the main object file. Also, this makes every object file format reimplement the idea of loading the interpreter. Admittedly only ELF recognizes and sets up an interpreter, but other formats conceptually could too. This does move that limitted hypothetical redundancy out of the object file formats and moves it into the process objects, but I think conceptually that's where it belongs. It would also probably be pretty easy to add a method to the base Process class that would handle loading an image and also the interpreter image. This change does not (yet) separate reading symbol tables. Change-Id: I4a165eac599a9bcd30371a162379e833c4cc89b4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21465 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-10-10arch, base: Stop assuming object files have three segments.Gabe Black
The ObjectFile class has hardcoded assumptions that there are three segments, text, bss and data. There are some files which have one "segment" like raw files, where the entire file's contents are considered a single segment. There are also ELF files which can have an arbitrary number of segments, and those segments can hold any number of sections, including the text, data and/or bss sections. Removing this assumption frees up some object file formats from having to twist themselves to fit in that structure, possibly introducing ambiguities when some segments may fulfill multiple roles. Change-Id: I976e06a3a90ef852b17a6485e2595b006b2090d5 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21463 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-10-09base: Rename Section to Segment, and some of its members.Gabe Black
ELF is, in my opinion, the most important object file format gem5 currently understands, and in ELF terminolgy the blob of data that needs to be loaded into memory to a particular location is called a segment. A section is a software level view of what's in a region of memory, and a single segment may contain multiple sections which happen to follow each other in memory. Change-Id: Ib810c5050723d5a96bd7550515b08ac695fb1b02 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/21462 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-05-30arch, base, cpu, gpu, sim: Merge getMemProxy and getVirtProxy.Gabe Black
These two functions were performing the same function but had two different names for historical reasons. This change merges them together, keeping the getVirtProxy name to be consistent with the getPhysProxy method used to get a non-translating proxy port. Change-Id: Idd83c6b899f9343795075b030ccbc723a79e52a4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18581 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2019-05-29sim-se: add a release parameter to Process.pyCiro Santilli
Set the default release to that single value for all ISAs. glibc has checks for the kernel version based on uname, and refuses to start any syscall emulation programs if those checks don't pass with error: FATAL: kernel too old The ideal solution to this problem is to actually implement all missing system calls for the required kernel version and bumping the release accordingly. However, it is very hard to implement all missing syscalls and verify compliance. Previously, we have simply bumped the version manually from time to time when major glibc versions started breaking. This commit alleviates the problem in two ways. Firstly, having a single kernel version for all versions means that it is easier to bump all versions at once. Secondly, it makes it is possible to set the release with a parameter, which in turn can be set from the command line with: se.py --param 'system.cpu[:].workload[:].release = "4.18.0"' Change-Id: I9e3c31073bfe68735f7b0775c8e299aa62b98222 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17849 Maintainer: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-29arch, base, dev, sim: Remove now unnecessary casts from PortProxy methods.Gabe Black
Change-Id: Ia73b2d86a10d02fa09c924a4571477bb5f200eb7 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18572 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2019-05-21sim-se: change syscall function signatureBrandon Potter
The system calls had four parameters. One of the parameters is ThreadContext and another is Process. The ThreadContext holds the value of the current process so the Process parameter is redundant since the system call functions already have indirect access. With the old API, it is possible to call into the functions with the wrong supplied Process which could end up being a confusing error. This patch removes the redundancy by forcing access through the ThreadContext field within each system call. Change-Id: Ib43d3f65824f6d425260dfd9f67de1892b6e8b7c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/12299 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Brandon Potter <Brandon.Potter@amd.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-05-20power: Add an object file loader for linux.Gabe Black
Change-Id: I64ce81e98a6dc96754554d0fdcd7d16b8a2752d4 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18587 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Sandipan Das <sandipan@linux.ibm.com>
2019-04-30arch: Stop using TheISA within the ISAs.Gabe Black
We know for sure what the ISA is, so there's no need for the indirection. Change-Id: I73ff04c50890d40a4c7f40caeee746b68b846cb3 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18488 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
2019-04-28arch, sim: Simplify the AuxVector type.Gabe Black
The AuxVector type has a bunch of accessors which just give access to the underlying variables through references. We might as well just make those members accessible directly. Also, the AuxVector doesn't need to handle endianness flips itself. We can tell the byteswap mechanism how to flip an AuxVector, and let it handle that for us. This gets rid of the entire .cc file which was complicated by trying to both hide the ISA specific endianness translations, and instantiate templated functions in a .cc. Change-Id: I433cd61e73e0b067b6d628fba31be4a4ec1c4cf0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18373 Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
2019-03-25arch-power: Rename program counter registersSandipan Das
The Power ISA specification lists the Program Counter (PC) and the Next Program Counter (NPC) registers as Current Instruction Address (CIA) and Next Instruction Address (NIA). This applies the ISA naming convention for these two registers. Change-Id: I8b9094ab1c809f4dfdb4d7330c17f360adf063e9 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16603 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-03-25arch-power: Simplify doubleword operand typesSandipan Das
Currently, 'sq' and 'uq' are used to represent signed and unsigned doublewords respectively. Since all recent Power ISA specifications list 128-bit quadwords as a valid data type, it may be misleading to use the current terminology in case support for such operands are added in the future. So, to simplify this, 'sd' and 'ud' are used to represent signed and unsigned doublewords respectively. Change-Id: Ie7831c596fc8f9ddfdf3b652c37cfe26484ebe01 Signed-off-by: Sandipan Das <sandipan@linux.ibm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16602 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-02-12python: Don't assume SimObjects live in the global namespaceAndreas Sandberg
The importer in Python 3 doesn't like the way we import SimObjects from the global namespace. Convert the existing SimObject declarations to import from m5.objects. As a side-effect, this makes these files consistent with configuration files. Change-Id: I11153502b430822130722839e1fa767b82a027aa Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/15981 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2019-02-01cpu, arch: Replace the CCReg type with RegVal.Gabe Black
Most architectures weren't using the CCReg type, and in x86 and arm it was already a uint64_t. Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6 Reviewed-on: https://gem5-review.googlesource.com/c/14515 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31power: Get rid of some ISA specific register types.Gabe Black
Change-Id: If63acb10705a9f442255680917d16630748ca8e1 Reviewed-on: https://gem5-review.googlesource.com/c/14465 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-31arch: cpu: Rename *FloatRegBits* to *FloatReg*.Gabe Black
Now that there's no plain FloatReg, there's no reason to distinguish FloatRegBits with a special suffix since it's the only way to read or write FP registers. Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded Reviewed-on: https://gem5-review.googlesource.com/c/14460 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-30arch,cpu: Add vector predicate registersGiacomo Gabrielli
Latest-gen. vector/SIMD extensions, including the Arm Scalable Vector Extension (SVE), introduce the notion of a predicate register file. This changeset adds this feature across architectures and CPU models. Change-Id: Iebcadbad89c0a582ff8b1b70de353305db603946 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13715 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-01-24base: arch: Get rid of the now unused FloatRegVal type.Gabe Black
This type is no longer used since FP registers are accessed as integer bit patterns. Change-Id: I1070f9443d6247165fd64c6bc041811c28287e9f Reviewed-on: https://gem5-review.googlesource.com/c/14459 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2019-01-22arch: cpu: Stop passing around misc registers by reference.Gabe Black
These values are all basic integers (specifically uint64_t now), and so passing them by const & is actually less efficient since there's a extra level of indirection and an extra value, and the same sized value (a 64 bit pointer vs. a 64 bit int) is being passed around. Change-Id: Ie9956b8dc4c225068ab1afaba233ec2b42b76da3 Reviewed-on: https://gem5-review.googlesource.com/c/13626 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
2019-01-22sim-se: add syscalls related to pollingBrandon Potter
Fix poll so that it will use the syscall retry capability instead of causing a blocking call. Add the accept and wait4 system calls. Add polling to read to remove deadlocks that occur in the event queue that are caused by blocking system calls. Modify the write system call to return an error number in case of error. Change-Id: I0b4091a2e41e4187ebf69d63e0088f988f37d5da Reviewed-on: https://gem5-review.googlesource.com/c/12115 Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2019-01-16arch: Make the ISA register types aliases for the global types.Gabe Black
The ISA specific types can thus be phased out. Change-Id: I8ea531a099fad140a4ec9c91cd972fe044111d60 Reviewed-on: https://gem5-review.googlesource.com/c/13623 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-10-17arch: Get rid of the unused type AnyReg.Gabe Black
This type is defined for all the ISAs but isn't used by anything. Change-Id: I659a0c5abc7883d82fedd1cac2cd103612d315c8 Reviewed-on: https://gem5-review.googlesource.com/c/13539 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-09-19syscall_emul: expand AuxVector classBrandon Potter
The AuxVector class is responsible for holding Process data. The data that it holds is normally setup by an OS kernel in the process address space. The purpose behind doing this is to pass in information that the process will need for various reasons. (Check out the enum in the header file for an idea of what the AuxVector holds.) The AuxVector struct was changed into a class and encapsulation methods were added to protect access to the member variables. The host ISA may have a different endianness than the simulated ISA. Since data is passed between the process address space and the simulator for auxiliary vectors, we need to worry about maintaining endianness for the right context. Change-Id: I32c5ac4b679559886e1efeb4b5483b92dfc94af9 Reviewed-on: https://gem5-review.googlesource.com/12109 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
2018-06-11misc: Using smart pointers for memory RequestsGiacomo Travaglini
This patch is changing the underlying type for RequestPtr from Request* to shared_ptr<Request>. Having memory requests being managed by smart pointers will simplify the code; it will also prevent memory leakage and dangling pointers. Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10996 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
2018-05-08arch-x86, arch-power: fix calls to bits and insertBitsMatt Sinclair
The bits and insertBits assume the first bit is the larger bit and the last bit is the smaller bit. This commit fixes several X86 and Power calls to these functions that incorrectly assumed that first was the smaller bit. Change-Id: I2b5354d1b9ca66e3436c4a72042416a6ce6dec01 Reviewed-on: https://gem5-review.googlesource.com/10241 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-26arch: Fix all override related warnings.Gabe Black
Clang has started(?) reporting override related warnings, something gcc apparently did before, but was disabled in the SConstruct. Rather than disable the warnings in for clang as well, this change fixes the warnings. A future change will re-enable the warnings for gcc. Change-Id: I3cc79e45749b2ae0f9bebb1acadc56a3d3a942da Reviewed-on: https://gem5-review.googlesource.com/9343 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-26arch: Add a virtual asBytes function to the StaticInst class.Gabe Black
This function takes a pointer to a buffer and the current size of the buffer as a pass by reference argument. If the size of the buffer is sufficient, the function stores a binary representation of itself (generally the ISA defined instruction encoding) in the buffer, and sets the size argument to how much space it used. This could be used by ISAs which have two instruction sizes (ARM and thumb, for example). If the buffer size isn't sufficient, then the size parameter should be set to what size is required, and then the function should return without modifying the buffer. The buffer itself should be aligned to the same standard as memory returned by new, specifically "The pointer returned shall be suitably aligned so that it can be converted to a pointer of any complete object type and then used to access the object or array in the storage allocated...". This will avoid having to memcpy buffers to avoid unaligned accesses. To standardize the representation of the data, it should be stored in the buffer as little endian. Since most hosts (including ARM and x86 hosts) will be little endian, this will almost always be a no-op. Change-Id: I2f31aa0b4f9c0126b44f47a881c2901243279bd6 Reviewed-on: https://gem5-review.googlesource.com/7562 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-20arch, mem: Make the page table lookup function return a pointer.Gabe Black
This avoids having a copy in the lookup function itself, and the declaration of a lot of temporary TLB entry pointers in callers. The gpu TLB seems to have had the most dependence on the original signature of the lookup function, partially because it was relying on a somewhat unsafe copy to a TLB entry using a base class pointer type. Change-Id: I8b1cf494468163deee000002d243541657faf57f Reviewed-on: https://gem5-review.googlesource.com/7343 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-20sim, arch, base: Refactor the base remote GDB class.Gabe Black
Fold the GDBListener class into the main BaseRemoteGDB class, move around a bunch of functions, convert a lot of internal functions to be private, move some functions into the .cc, make some functions non-virtual which didn't really need to be overridden. Change-Id: Id0832b730b0fdfb2eababa5067e72c66de1c147d Reviewed-on: https://gem5-review.googlesource.com/7422 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-19arch, mem, sim: Consolidate and rename the SE mode page table classes.Gabe Black
Now that Nothing inherits from PageTableBase directly, it can be merged into FuncPageTable. This change also takes the opportunity to rename the combined class to EmulationPageTable which lets you know that it's specifically for SE mode. Also remove the page table entry cache since it doesn't seem to actually improve performance. The TLBs likely absorb the majority of the locality, essentially acting like a cache like they would in real hardware. Change-Id: If1bcb91aed08686603bf7bee37298c0eee826e13 Reviewed-on: https://gem5-review.googlesource.com/7342 Reviewed-by: Brandon Potter <Brandon.Potter@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-15arch: Fix a fatal_if in most of the arch's process classes.Gabe Black
When switching an assert to a fatal while addressing recent review feedback, I forgot to reverse the polarity of the condition, making the fatal fire in exactly the opposite of the conditions it was meant to. Change-Id: Icf49864ef449052bbb0d427dca786006166575c4 Reviewed-on: https://gem5-review.googlesource.com/7381 Reviewed-by: Matthias Jung <jungma@eit.uni-kl.de> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2018-01-11arm, power: Make the python TLB simobjects inherit from BaseTLB.Gabe Black
These were still inheriting from SimObject instead of BaseTLB, making them incompatible with parameters which expect a BaseTLB. Change-Id: I05115cc5515f745fdeb85e4dea8eded613647e40 Reviewed-on: https://gem5-review.googlesource.com/7348 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
2018-01-11arch,mem: Remove the default value for page size.Gabe Black
This breaks one more architecture dependence outside of the ISAs. Change-Id: I071f9ed73aef78e1cd1752247c183e30854b2d28 Reviewed-on: https://gem5-review.googlesource.com/6982 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
2018-01-11arch,mem: Move page table construction into the arch classes.Gabe Black
This gets rid of an awkward NoArchPageTable class, and also gives the arch a place to inject ISA specific parameters (specifically page size) without having to have TheISA:: in the generic version of these types. Change-Id: I1412f303460d5c43dafdb9b3cd07af81c908a441 Reviewed-on: https://gem5-review.googlesource.com/6981 Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-10style: change C/C++ source permissions to noexecBKP
Several files in the repository were tracked with execute permissions even though the files are just normal C/C++ files (and the one .isa). Change-Id: I976b096acab4a1fc74c5699ef1f9b222c1e635c2 Reviewed-on: https://gem5-review.googlesource.com/7241 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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