| Age | Commit message (Expand) | Author |
|---|---|---|
| 2019-01-31 | riscv: Get rid of some ISA specific register types. | Gabe Black |
| 2019-01-16 | arch-riscv: Add interrupt handling | Alec Roelke |
| 2019-01-16 | arch-riscv: Fix reset function and style | Alec Roelke |
| 2018-07-28 | arch-riscv: Add xret instructions | Alec Roelke |
| 2018-07-28 | arch-riscv: Add support for trap value register | Alec Roelke |
| 2018-07-28 | arch-riscv: Add support for fault handling | Alec Roelke |
| 2018-07-09 | arch-riscv: enable rudimentary fs simulation | Robert |
| 2017-07-14 | riscv: Fix bugs with RISC-V decoder and detailed CPUs | Alec Roelke |
| 2016-11-30 | riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD | Alec Roelke |
| 2016-11-30 | arch: [Patch 1/5] Added RISC-V base instruction set RV64I | Alec Roelke |
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| gem5 |
| summaryrefslogtreecommitdiff |