gem5 - gem5

Age	Commit message (Collapse)	Author
2018-07-28	arch-riscv: Add support for trap value register	Alec Roelke
	RISC-V has a set of CSRs that contain information about a trap that was taken into each privilegel level, such as illegal instruction bytes or faulting address. This patch adds that register, modifies existing faults to make use of it, and adds a new fault for future use with handling page faults and bad addresses. Change-Id: I3004bd7b907e7dc75e5f1a8452a1d74796a7a551 Reviewed-on: https://gem5-review.googlesource.com/11135 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <alec.roelke@gmail.com>
2018-05-12	arch-riscv: Update CSR implementations	Alec Roelke
	This patch updates the CSRs to match the RISC-V privileged specification version 1.10. As interrupts, faults, and privilege levels are not yet supported, there are no meaninful side effects that are implemented. Performance counters are also not yet implemented, as they do not have specifications. Currently they act as cycle counters. Note that this implementation trusts software to use the registers properly. Access protection, readability, and writeability of registers based on privilege will come in a future patch. Change-Id: I1de89bdbe369b5027911b2e6bc0425d3acaa708a Reviewed-on: https://gem5-review.googlesource.com/7441 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2018-03-26	arch: Fix all override related warnings.	Gabe Black
	Clang has started(?) reporting override related warnings, something gcc apparently did before, but was disabled in the SConstruct. Rather than disable the warnings in for clang as well, this change fixes the warnings. A future change will re-enable the warnings for gcc. Change-Id: I3cc79e45749b2ae0f9bebb1acadc56a3d3a942da Reviewed-on: https://gem5-review.googlesource.com/9343 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-03-26	arch: Add a virtual asBytes function to the StaticInst class.	Gabe Black
	This function takes a pointer to a buffer and the current size of the buffer as a pass by reference argument. If the size of the buffer is sufficient, the function stores a binary representation of itself (generally the ISA defined instruction encoding) in the buffer, and sets the size argument to how much space it used. This could be used by ISAs which have two instruction sizes (ARM and thumb, for example). If the buffer size isn't sufficient, then the size parameter should be set to what size is required, and then the function should return without modifying the buffer. The buffer itself should be aligned to the same standard as memory returned by new, specifically "The pointer returned shall be suitably aligned so that it can be converted to a pointer of any complete object type and then used to access the object or array in the storage allocated...". This will avoid having to memcpy buffers to avoid unaligned accesses. To standardize the representation of the data, it should be stored in the buffer as little endian. Since most hosts (including ARM and x86 hosts) will be little endian, this will almost always be a no-op. Change-Id: I2f31aa0b4f9c0126b44f47a881c2901243279bd6 Reviewed-on: https://gem5-review.googlesource.com/7562 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-29	riscv: Add overrides to various StaticInst methods.	Gabe Black
	This makes riscv compile with the version of clang(++) I have on my workstation. Change-Id: I0478616810fbc8a715fd61323b7e0f73676c8328 Reviewed-on: https://gem5-review.googlesource.com/7643 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Gabe Black <gabeblack@google.com>
2018-01-11	arch-riscv: Don't crash when printing unknown CSRs	Alec Roelke
	This patch fixes a potential crash if an unnamed CSR is accessed and debug flags are enabled that print disassembly. Unknown CSRs will be identified as "??" followed by the address that was used. Change-Id: If5ac57f1422bd59c72a1a06206fa9d9dc05d21ef Reviewed-on: https://gem5-review.googlesource.com/7321 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-12-07	arch-riscv: Move compressed ops out of ISA	Alec Roelke
	This patch moves static portions of the compressed instruction definitions out of the ISA generated code. Change-Id: I61daae8b8c03a9e0f012790a132aa4d34a6ec296 Reviewed-on: https://gem5-review.googlesource.com/6026 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-29	arch-riscv: Add missing license paragraphs	Alec Roelke
	Some of the files in earlier patches rearranging instruction definitions were missing copyright and license information. This patch adds them. Change-Id: I2ac4910a415de6032fc0b7d4422904c682e0ad87 Reviewed-on: https://gem5-review.googlesource.com/6183 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
2017-11-29	arch-riscv: Remove static parts of AMOs out of ISA	Alec Roelke
	This patch removes the static parts of the RISC-V atomic memory instructions out of the ISA generated code and into arch/riscv/insts. It also makes the LR and SC instructions subclasses of MemInst from arch/riscv/insts/mem.hh. Change-Id: I6591f3d171045c4f1b457eb1264bbb7bd62b3e51 Reviewed-on: https://gem5-review.googlesource.com/6025 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-29	arch-riscv: Move parts of mem insts out of ISA	Alec Roelke
	This patch moves static portions of the memory instructions out of the ISA generated code and puts them into arch/riscv/insts. It also simplifies the definitions of load and store instructions by giving them a common base class. Change-Id: Ic6930cbfc6bb02e4b3477521e57b093eac0c8803 Reviewed-on: https://gem5-review.googlesource.com/6024 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-29	arch-riscv: Move unknown out of ISA description	Alec Roelke
	This patch removes the Unknown instruction type out of the ISA generated code and puts it into arch/riscv/insts. Since there isn't any dynamic behavior to it, all that's left behind is a template for creating a new Unknown instruction. Change-Id: If7c3258a24ecadd3e00ab74586e1740e14f028db Reviewed-on: https://gem5-review.googlesource.com/6023 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-29	arch-riscv: Move standard ops out of ISA	Alec Roelke
	This patch removes static portions of the standard instruction types from the generated ISA code and puts them into arch/riscv/insts. Some dynamically-generated content is left behind for each individual instruction's implementation. Also, BranchOp is removed due to its similarity with ImmOp and ImmOp and UImmOp are joined into a single templated class, ImmOp<T>. Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a Reviewed-on: https://gem5-review.googlesource.com/6022 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>
2017-11-28	arch-riscv: Move static_inst into a directory	Alec Roelke
	This patch creates an "insts" directory in src/arch/riscv to store static portions of instruction definitions that aren't part of the code generated by the ISA description. It serves as a starting point for future patches to simplify the ISA description. Change-Id: I6700522143f6fa6c9b18a30e1fbdc8f80cdc7afa Reviewed-on: https://gem5-review.googlesource.com/6021 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Alec Roelke <ar4jc@virginia.edu>